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TPS61196: how to reduce heat on Q1 and duty cycle question

Part Number: TPS61196

Hey guys,

My switching FET gets incredibly hot and my heat sink has to be massive which makes me think I've done something wrong. 

Is it the nature of this architecture? All the heat is in the FET (STP70N10F4  has RdsON 0.0195ohm at 60A). I see the duty cycle is around 75% (measured at GDRV) which matches the equation used to size up your output cap. I understand that this means I have my power supply sourcing current that gets shunted to ground for this time period (can you confirm?). I can increase my Vin voltage to help out(go from 12 to 24V). I was wondering if there was other design tweaking that could be done or common tricks you might be aware of or other? I have 2 designs I’m using this on. One is 10W and everything is nice and cool. My 50W design needs a massive heat sink on the FET. Both designs optimize routing planes and make other considerations for the power paths. Both designs are stable and switch consistently. My R7 has been sized a little above the I(Ldc)+I(Lpp). Thanks for any comments. 

Thanks!

  • Hi Jacob,

    Basically, there are several ways to reduce the power loss on MOSFET. To reduce the conductive loss, a low Rds(on) MOSFET is a good choise, and you already did that. To reduce switching loss, you could reduce the switching frequency. To reduce turn-on/turn-off loss, you could accelerate the turn-on and turn-off speed. For example, you could reduce the driven resistor value, or you could add a diode in parallel with driven resistor to accelarate the turn-off speed. Hope this could help you a bit.

  • Hi, Thanks for the reply. Do you mean that i have this excessive heat due to turn on/off loss? I can run an experiment with R19 and see what happens.

    When it is on, i have ~3.5A going through L1, Q1, R7. I'll also build a circuit and dissipate the 3.5A through this same network and see how the heat compares with no switching.