• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 64 subscribers
  • Views 935 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS65381A-Q1: Output condition of ENDRV at Power-up

Shinichi Inoue
Guru 21646 points
Part Number: TPS65381A-Q1

Dear Specialists,

My customer is considering TPS65381A-Q1 and has a question.

Could you please advise?

---question---

According to the datasheet P.23 (5.4.1 Power-Up and Power-Down Behavior) of Figure 5-1. Power-Up and Power-Down Behavior,

ENDRV signal begins LO.

Is there any possibility when the device starts working(power on),  it outputs intermediate  voltage and then LO?

Could I decide always LO? 

---

I appreciate your great help in advance.

Best regards,

Shinichi

  • 0
    TI__Genius 9380 points
    Shinichi,
    I have taken some time to look at your customers question. It may not as straight forward as that as the ENDRV pin has quite the state machine behind it. I am passing your question to a specialist for review. If you can explain any details or add more information, it would help to answer your question.
  • 0
    TI__Mastermind 20590 points

    Hi Shinichi,

    Yes, you can decide it is low from the device viewpoint and the normal assumed use case it will remain low.  The background is following.  As the TPS65381A-Q1 was powered down the previous power cycle, the ENDRV open drain FET would have pulled the output low. When TPS65381A-Q1 is unpowered, the pin will be floating internally (pull up VDDIO off and open drain FET off), but will have been discharged low previously. As TPS65381A-Q1 powers up, the internal rail on the device power up first and will then turn the pull down FET of the ENDRV circuit on so the ENDRV driven low.  Then the rails of the device ramp up.  It is assumed either VDD5 or VDD3/5 is used to supply the VDDIO to the device so there would be a pull up path only after the device has already internally powered up and is driving the ENDRV low.   Additionally the external input circuits attached to the ENDRV such as a power stage disable input or MCU GPIO used to monitor the ENDRV signal could have integrated pull downs so the line could not float when the TPS65381A-Q1 is unpowered.  If these inputs do not have an integrated pull down then an external weak pull down could be added to keep the line low if necessary.  If the ENDRV line is pull up to any source that is not supplied by the TPS65381A-Q1 the special consideration would need to be taken at the system level.

    Best Regards,

    Scott

  • 0 in reply to Gordon Varney
    Guru 21646 points
    Hi Gordon

    Thank you for your reply and arrange.

    I appreciate your great help and cooperation.

    Best regards,
    Shinichi
  • 0 in reply to Scott Monroe
    Guru 21646 points
    Hi Scott,

    Thank you for your reply and explanation in detail.

    I send your answer to the customer.

    If he has an additional question, I'll consult you.

    I appreciate your great help and cooperation.

    Best regards,
    Shinichi