WEBENCH® Tools/LMR14050: Webench SimExport to Tina-TI -- design fails to perform

Hi Chris,

Why you use 3x220uF as Cout? normally one 220uF is good enough for 12V/2.5A even with Fsw 400KHz.

The circuit may works in current limit mode if Vout doesn't ram up to target value after soft start time finished, tha't what you see in TINA simulation, this is cause by Css cap is too small and Cout is too big,

Pls change Css to 68nF and use resistor load instead of CC load for TINA simulation.

B R
Andy

Andy,

The starting point for this design comes from an earlier Webench LMR14050Q1-DPR design (possibly at 3A, 85C) that suggested 2x 390uF conductive polymer aluminum capacitors (I suppose for their very low ESR).  I use 3x 270uF to get the same low ESR effect.  My design may be overkill but my user has not defined the load requirements very well, and I need to have a robust output.

As for the LMR14050 model exported to Tina:  I have found that there is no trouble getting to 12.0V at the output if the feedback resistor ratio is altered.  This is because the model has 0.575V for its internal reference -- not 0.750V.  Please check this with your modeling group.  I think you will agree with me.

Another model issue is that the Enable input does not have any hysteresis, UVLO, functionality.  Although simulating startup with an Enable divider is next to impossible, it is possible to have the input rise quickly and fall slowly to see the incorrect UVLO value, with the divider in place.

I use the 4.7nF Css value as it is the maximum prescribed in the datasheet for the LMR14050-Q1 and the WSON package (my target design).  I do find it odd that the package dictates this requirement, as I'd like to have a larger soft-start capacitor as well.  There must be some instability in the design.

  "For LMR14050-Q1 in WSON package, the maximum value of CSS is 4.7 nF"

There is no constant current load in my simulation, the 4.8 Ohm resistor load was exported as a macro from Webench.  Please review my earlier and current schematic.webench_design_661398_35 50mS 06-20a.pdf

Here is my latest schematic with some notes (Tina design, nearly the same as I sent earlier) and a plot of the output.  As you can see it has significant peak-to-peak ripple/noise.  The Tina result is very disconcerting.webench_design_661398_35 LMR14050 2.5A 400kHz Startup.TSC

 

Andy,

I must change my reply.  And I apologize for jumping to conclusions based on observations of changing the feedback.

It turns out that a large Cout can cause this significant problem.  If my unknown load is more capacitive will this issue occur in a physical circuit?  How can I make the circuit more robust and tolerant of a larger load capacitance?

BR - Chris

Chris,

Do you have to use WSON package part? you may have two options:

1. Select SO8 package and use big Css cap for proper startup with big Cout
2. Use WSON package and Cout below 440uF, Eanble downstream load by PowerGood signal of LMR14050.

WSON package has limitation on Css because of little different Pin-out compared with SO8 package.

Soft start time is about 1ms for Css=4.7nF, if Vout=12V, Cout=440uF, then you can calculate the minimum current to charge up Cout in 1ms:
Iout=Cout*Vout/Tss=440u*12V/1ms=5.28A, this is just the maximum output current of LMR14050.

If you don't want to use PowerGood signal, then program the enable voltage of down stream load at about 10V. (Ren-top=768K, Ren-bot=107K, hysteresis=2V)

EN pin hysteresis is generated by resistor divider connected to EN pin, pls refer to data sheet 7.3.6 section.

B R
Andy

Andy,

Yes, I plan on using the Enable with hysteresis, but not for PowerGood purposes.  It is required for input voltage sensing.  I have it set for my other requirements.   It seems that this will not affect the way the LMR14050 responds to the load, simply at which voltage to start the oscillator.  The PowerGood approach with a PFET seems to be the best way.

As I mentioned earlier, it is not possible to demonstrate the Enable feature (simulations continually fail with a slow rise time) with the enable resistors set (Rent=348K, Renb=29.4K -- Start=15.06V, Stop=13.80V), I can see the UVLO feature though (fast input voltage rise with a slow decline), and it is at the same voltage that I set for the power on, so there is no hysteresis in the model.  Maybe you can test this.

Adding a series element for load switching will add heat, cost and power loss, unfortunately.  The WSON package is better at dissipating heat and I am trying to make a very robust design.  It seems we can't have it all.

Simulations do show that with Css = 10nF it will start up with heavy loading (1945uF), it settles at 12V after some time of noisy oscillation getting there (at 35mS) -- see attached.  Must the max current and soft start time always be matched to the load capacitance as you mentioned above?  Or is full output much later in time than the soft start time reasonable?  I don't care if it takes over 100mS to start -- as long as it always starts.LMR14050 661398_35 2.5A 400kHz 10nF,1945uF.pdf

Regards,

Chris

Hi Chris,

For NO LOAD condition, the output always can ramp up no matter how the soft start time is short and total Cout is huge, but the output may ramp up unsmoothly with some oscillation as you see in simulation. No Load means no resistor or CC mode E-load connect to output.

Can you program the enable voltage of the loads connected to LMR14050 output? or use LMR14050 PowerGood signal to enable the loads? this will makes the LMR14050 startup at no load condition.

Pls feel free to send email to me for further discussion.

B R

Andy

Email: andy.chen@ti.com