• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 63 subscribers
  • Views 434 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS51315 - Ultra Low Ouput ESR and Instability

Brian Faunce
Prodigy 10 points

I am currently using a TPS 51315 which is stepping down 7V to 1.2V with a maximum output current of 7.5A.  The power supply is driving 32 FPGA's which require over 200 ceramic decoupling capacitors along with several tantalum capacitors.  I know that the equivalent ESR of all of these capacitors will cause instability issues so I need to know how, if there is a way, to stabilize the circuit.  The data sheet says "refer to figure 29" for the "few external components" that need to be added to the circuit to make it stable with ceramic ouput capacitors, but it does not explicitly say which components are required or how to calculate their values.  Any help would be greatly appreciated,

           - Brian Faunce

  • 0
    TI__Guru 56925 points

    Brian,

     

    Here is a process I've used to calculate these component values:

    1) Determine the ESR required on the output capacitance to maintian the required ESR zero less than 1/5 the switching frequiency:

      ESR(min) = 5 / (2 * pi * Cout * Fsw)

    2) Determine the output voltage ripple produced by that ESR

      Vrip = (Vin-Vout * Vout/Vin * 1/Fsw)  * ESR / L  - The first term is Vin-Vout * Ton, or the volt-seconds applied to the inductor during the On-time

    3) Scale this ripple to the feedback pin

      Vrip(fb) = Vrip * Vref / Vout OR Vtrip(fb) = Vrip * Rbias / (Rfb + Rbias)   - Rfb is the resistor from Vout to FB and Rbias is the resistor from FB to GND

    4) Select a capacitor (10nF - 100nF works well) and calculate the resistor for an R-C across the inductor to produce this ripple.

      Rrc = Vout/Vref * L / (ESR * Crc)  - Rrc and Crc are the R-C from the switching node to the output voltage.  The capacitor must be connected to the ouput voltage.

    5) Determine the impedance looking into the feedback pin.

      Rfb(eq) = 1 / ( 1/ Rfb + 1/ Rbias)

    6) Size a DC blocking capacitor between the junction of Rrc & Crc and the FB node

      Cblocking = 5 / (2 * Pi * Rfb(eq) * Fsw)

    The ripple injection from Rrc & Crc will add a load-line to the feedback signal that will be removed by Cblocking.  Cblocking and the impedance into the feedback node will determine the time-constant of the removal of this load line.  Increasing Cblocking will slow the recovery from this load line (equal to delta Iout * DCR).  Decreasing the blocking capacitor will speed up this response time, but may also cause over-shoot on recovery.  Time constants less than 5x the switching period (the equation used above) are not recommended.  Large time constants, upto a few hundred micro-seconds can be chosen.  The time constant should be less than 1/3 the required settling time of the ouptut voltage.

    If a load line equal to the DCR of the inductor is acceptable, the DC blocking capacitor can be eliminated and the feedback divider can be moved to the junction of Rrc and Crc and Rrc and Crc can be sized by: Rrc = L / (ESR * Crc).  In this case Rfb and Rbias should be at least 10x Rrc to minimize the impact of their leakage current on the programming accuracy of the output voltage.

    Since this will impose a load line equal to the DCR of the inductor, it may be desirable to shift the no-load operating point up by 1/2 Iout(max) * DCR such that nominal operating point is achieved at mid load, and the operarting voltage rises and falls equally over the full load range.