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TPS54020: questions about regulator operation

Part Number: TPS54020

Hello,

I'd like to implement tracking and AVS functions with TI's TPS54020RUWR regulator. (PON chip requirement.)

Can you share common applications of schematics?

Eight TPS54020RUWRs should be supplied to each of the eight chips in total, with 1.0V, and the following functions should be included.

1) 3.3V tracking (3.3V output from other regulator should be 1.0V power-up at the same time, 0.1V-> 0.2V-> 0.3V at the same time.
The datasheet 16 page describes how to implement the related functions. I do not know if it is accurate. Please confirm.)
2) AVS function (connect PVTMON_ADC of PON chip to feedback pin of regulator. I do not know which pin is used for feedback function.
  Please confirm.)

TPS54020RUWR
Each input voltage: 12V
Each output voltage / Max current: 1.0V / 7.476A

3.3V tracking

HW structure between PON chip <-> regulator for AVS implementation is as follows.

I have a question. In the datasheet, what exactly are the resistances of R upper and R lower?

The TI simulation results are shown below.

The power structure is as follows.

thanks,

TS

  • 1. So far as I know, the equations in the tracking section of the datasheet are accurate.
    2. the FB function pin is named VSENSE. It is pin 13.

    There is a reference design on this page:
    ti.com/product/TPS54020/toolssoftware

    And The EVM Users guide is here:
    www.ti.com/.../slvu777

    Rupper and Rlower are the feedback resistors that set the output voltage. They are the same as Rfbt and Rfbb in the Webench schematic.
  • Hello,

    thanks for your kind answer.

    Here's some additional questions.

    Why does the R bottom value range have to be between 1kohm and 3khom?

    What is the problem with the R bottom value of 15Kohm?

    The R top required to implement the AVS function required on the chip is more than 9kohm, and the R bottom value to match Voutput 1.0V is more than 15Kohm.

    I wonder whether the following chip AVS HW setting can not be applied with TPS54020RUWR.

    For reference, the load specification of the power supply is as follows.

    Each output voltage / Max current: 1.0V / 7.476A

    thanks,

    TS

  • The answer to your question is in the following sentence..."During light load conditions, this resistor range provides enough load current to exceed the bias leakage current that may be sourced by the PH pin. I think you can use larger resistor values if you never operate at light loads.
  • I would like to request a review of the below attached TI Power.

    TI power review.pdf

    1. load conditions: each input voltage: 12V / each output voltage: 1.0V / output current rms: 7.476A,

    Output efficiency: 90% or more
    Output voltage accuracy: +/- 2%

    2. power sequence : ratio-metric and simultaneous startup sequence ; tracking 3.3V (net name : VCC_3_3)- see the figure below

    We will ask you to:
    1. Schematic review result
    2. Output efficiency (1.0V) waveform
    3. Output waveform (3.3V, 1.0V x8)

    thanks,

    TS

  • Do you have the equations or methodology (Webench, etc) used to calculate the component values?  If you provide them I can check your schematic.  Otherwise I can only look for obvious mistakes or unusually large or small component values.

  • Hi,

    The formula used depends on the type of sequence. Please confirm that the schematic I attached before is correct to be in the following sequence.

    The methodology used when calculating component values is as below.

    1. Refer to online simulate & Typical application.
      -> The input and output capacitor values are different from each other, I would like to ask what value would be better.

    Enter a value as below.

    Equations used when calculating component values.

    TPS54020

    Ratiometric and Simultaneous Startup Sequence equations

     

    ΔV = 0 (because, The ΔV variable is zero volts for simultaneous sequencing. )

    Vout1 = 3.3V (ß track target)

     

    When, Rtop =10kohm, Rbot = 14.3kohm,

    Vout2 = 1.0195V ß Equation 1

     

    RS1 > 9.24Kohm ß equation 8

     

    When, set RS1 = 12.7kohm,

    RS2 = 18.1kohm ß equation 6

     

    Set RS2 = 19.1kohm (only available resistor value)

     

    Thus,

    Rtop =10kohm

    Rbot = 14.3kohm

    RS1 = 12.7kohm

    RS2 = 19.1kohm  

    In addition, I have questions about artwork.

    In the typical application, designed GND by PGND and AGND as below. At what point exactly does PGND and AGND short?
    I would like to ask if it is better to keep VIN bypass and PVIN bypass apart as shown below.

    The PGND area and the AGND area are divided into separate planes as described below, and only connected to the vias, is that right what I understand?

    thanks,

    TS

  • Hello TI,

    I'm still waiting your answer.

    Please answer my additional questions about sequence, compenent values, and grounds.

    Thank you for your help always.

    TS
  • Hi,
    I am still waiting for an answer.
    Is it delayed because of the holiday season?
    Let me know if I need to write a new one.
  • First off you have to reverse the tracking order.  the lower voltage has to track the higher voltage.  In that case, I get 21.0 k for the top resistor and 31.52 k (31.6k std val).  Also there is a typo in EQ 5.  It should be Vout1 + deltaV, not Vout1 * deltaV.

    On the EVM the AGND and PGND are connected here on the back side at a single point:

  • Hello, TI

    We have set the values as shown below with reference to the comments you sent.

    1. Can RS1, RS2, Rtop, Rbot be applied to the following values?

    Hi I am Yoo Jae cheon. Dasan networks engineer.

     

    I am asking you again because there are still something confusing me.

     

    First, you mentioned a typo in EQ 5,

    You have changed two things at once.

    Vout2 à Vout1 ,

    and

    Vout1 * delta V à Vout1 + delta V.

     

    But in my calculation below, changing Vout2 à Vout1 in EQ 5 doesn’t seem to correct.  

    In my calculation, I guess Vout2 should be applied in EQ 5 in order to track 3.3V as you mentioned.

    (See the figure 21 below where Vout1 and Vout2 refers to)

     

    So I have applied Vout2 (1.0V) in EQ 5 instead of Vout1 (3.3V)

    And then I could have calculated exact same result as you did.

     

    Vss = 29mV, Iss =2.3uA, Vout2 = 1.0 V

     

    According to modified EQ 5,

    Register for Ratio-metric and Simultaneous Startup,

    RS1 = 21.014kohm, (which you mentioned as the top resistor) à 21kohm (standard)

    RS2 = 31.521kohm. , à 31.6kohm(standard)

     

     

    According to EQ 1



    Register for output voltage, Vout=1.0195V

    R4(Rupper) =10kohm

    R8(Rlower) = 14.3kohm


    2. I do not think there is any review on the circuit diagram I have given you before.Is it possible to design with the following structure?

    thanks,

    TS

  • Are you trying to design eight individual supplies, each with 1.0 V output?  Or are you wanting to connect all these in parallel and to combine the current for a single load?  You can certainly use the first approach.  TPS54020 is not designed to operate in  stackable current sharing application.

  • I calculated the simultaneous start up tracking resistor values as Rupper = 21.0 k and Rlower = 31.6 k.

    VSENSE (pin 13) is the feedback pin.

  • Sorry to confuse you. Eight TPS54020RUWR should be supplied to each of the eight chips. I mentioned this at the first of my question, but the word "in total" might cause confusion.
  • If each TPS54020 is supplying an independent load, then it will work.