Control strategy for a 3 phase asynchronous buck converter

Hello,

It’s a bit of an open ended question as this will certainly depend on the AC and DC losses. By AC, I am referring to things like Switching losses, Transitional Losses and Core Losses in your magnetics. And DC losses are referring to Conduction losses in your FETs, Diodes and DCR of your magnetics. The reason why it depends on this is because the ratio between these will dictate your Efficiency (y axis) vs. Load current (X axis) curve. For example if you have low AC losses, typically you will have higher DC losses due to the figure of Merit (FOM) between RDSon and Gate charge of the FETs selected, and the core losses being low, typically means a higher inductance which means more turns yielding higher DCR losses. What this does to your efficiency curve is it yields efficiency relatively higher at lower currents and lower at higher currents compared to the converse set up of lower DC losses and higher AC losses (Lower efficiency at light load and higher efficiency at high load currents). The reason why I am talking about this is because you ultimately want to phase shed at the point the efficiency curve starts to dip due to the AC losses. It is at this dip point that it is best suited to shed a phase. If I were you, I would design the shedding of phases circuit such that its adjustable and once you get your actual efficiency profile you can make the best determination of when to shed the load to maximize efficiency. Hope this helps you with a strategy going forward? Perhaps a pic paints a thousand words here, let me know if you follow what I am saying?

Picture paints a thousand words, please see attached.  Hope this makes sense

1447.Phase shed example.docx

Hi, 

this compensation goes mostly for analog design. I'm going to use a MCU do control it. 

Best regards, 

Marko

Hello Marko,

Try the POWERSTAGE-DESIGNER tool.

This allows you to experiment with different topologies.
You enter Vin Vout Iout Fswitch and a few other parameters.
The tool recommends a minimum inductance, calculates power stage voltages and currents.

But still this does not answer my original question, let me try to illustrate it better.  Lets say the L = 1.5mH, for 20kHz, I get the following:

The (3f) and so on,  show how many phases can be active to still be in a 30% IL ripple constraint.

But lets say that at 5KW at 400 V i would use 3 phases, that would but me into DCM. This is not desirable, right? Because if it is, then I could further reduce the inductance.

Hope this makes my question more clear.

Best regards,

Marko  

As the graph that David provided, the phases should be dropped when total system efficiency start to suffer.

You may be able to model the total system, PFC front end and multiphase DCDC.
Understand where the losses are.
Create graphs of efficiency at various loads to determine the points where you want to start shedding.
Its not just the DCDC's, but the front end must be considered for its contribution.

Bottom line is, you shed phases when you need to.

DCM operation is not undesirable.
The loop gain of a buck converter is reduced in DCM, slowing its transient response rate.
But DCM can be more efficient.

Many times you start shedding phases when the mosfet gate drive power and switching losses start to dominate at light load.
So the system phases will have CCM DCM, pulsed or off mode.

I would create a design prototype that is flexible so you can change components.
Do some testing; Efficiency Vs Vin Vs Vout Vs Iout, drop some phases and create an efficiency graph of the system.
With a uC in charge it can decide when to start shedding.

There will be some iteration in this process.

Thank you EdWalker, for your great explanation.

So then what parameter would you look at for choosing the inductor value? In my sistem ripple is non-critical. As the mass of the work peace being heated smooths all "fast" power variances.  

Would looking for a good bang for buck output capacitor - a good capacitance/max ripple current for price - and then choosing the inductors so that the capacitor ripple current does not exceed half the max current allowed be a good idea? 

E.G. Lets say that I have a capacitor for 40A ripple at 20 kHz and then I chose a inductor so that the ripple current (at worst case) is 20A. 

Best regards, 

Marko