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TPS65381-Q1: SPI Parity

Bob Bacon
Genius 10815 points
Part Number: TPS65381-Q1
Other Parts Discussed in Thread: RM48L952, HALCOGEN, TPS65381A-Q1

Hello
Could you help with following request

I am currently working on connecting RM48L952 dev board with TPS65381 evaluation board and wanted to ask about SPI parity.

I first run HalCoGen demo for “RM48L952_HitexKit”  from SafeTI Diagnostic Library and it worked fine, then I moved some basic get and set register functions from SefeTI library to my project, modified my projects HalCoGen configuration for MIBSPI to match the demo and it also worked fine.  

My problems started  when I  modified the HalCoGen configuration to match my requirements. When I enabled Parity in Data Formats tab my communication started to fail. In TPS65381 datasheet (SLVSDJ1A)  I found some information about Command parity but none about parity of whole transferred frame.

Is there any way to configure TPS chip for SPI with enabled parity, or is there some other mechanism for checking parity of whole frame (or data part of the frame)?

Many Thanks
Bob Bacon

  • 0
    TI__Intellectual 1360 points
    Bob,
    From my understanding of the spec, the parity bit is only for the command code and not for the whole frame. I have assigned this thread to device expert and he will let you know if there is way to configure it differently.
    Jay
  • 0
    TI__Mastermind 20590 points

    Hi Bob,

    There is no parity on the whole SPI frame for the TPS65381A-Q1.  Just a parity bit on the 7 bit command and from a certain viewpoint this could then be viewed as an 8 bit command.  The data portion of the SPI frame does not have parity.  To cover configuration registers there are a couple of protection mechanisms:  CRC8 for configuration registers.  During DIAGNOSTIC state when the device is configured the customer software calculates the CRC8 as outlined in the datasheet for the covered registers and stores this CRC into SAFETY_CFG_CRC register.  Then the MCU can periodically re-run the CRC check in the TPS65381A-Q1 as outlined in the Device Configuration Register Protection section of the datasheet to make sure the configuration registers were configured properly and have not changed. Alternatively an even better diagnostic approach is write followed by read to make sure the intended data was even shifted into the registers properly which is much higher diagnostic coverage than a parity bit which covers only parity on the SPI shift.  For SDO read back data there is the SDO error indicated for a previous SPI frame by the STAT[2] bit received in the device status flag byte response.  This bit is set any time the TPS65381A-Q1 SDO read back doesn't match what it is trying to send on SDO.

    Best Regards,

    Scott