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TPS40140 SS Delay Time

Samuel Fritzinger
Prodigy 190 points
Other Parts Discussed in Thread: TPS40140

I am enabling the output voltage of the TPS40140 by releasing the UVLO pin from a pull-down to ground.  When I do this I see about  a 3.5ms delay before the output starts to rise.  What is the minimum and maximum time that I can expect to see for this delay?

thnx,

Sam

  • 0
    TI__Guru 56925 points

    Sam,

     

    We don't specify this and we don't test it, so estimates will be a little rough.  There are main 3 components to this:

     

    1) The charing of the 5V regulator's capacitor.  Since the regulator is disabled when the controller is disabled, the 5V regulator will need to charge before the controller enables.  This timing will depend on the current available from the regulator, which should be 80-150mA during this charge phase.

    2) Once the UVLO on the 5V regulator is released, there are several additional internal "Power OK" signals that need to be met.  This includes band-gap, oscillator and a few internal reference voltages that need to be stablized to ensure proper operation.  This typically adds an addition 0.5 - 1.5ms of start-up delay.

    3) Once all of the internal power OK signals have been asserted, there is a 1024 master clock cycle "Soft-Start Wait" timer.  The master clock runs at 8x the phase clock, so this is approximately 256 cycles of a phase clock.

    After those three delays, the soft-start voltage should being to rise.  In all, expect to see a start-up delay of 0.5ms + 256 phase clock cycles to 4ms + 256 phase clock cycles, with the size of 5V regulator capacitor having some influence over that delay.

    There may be some additional delay in the rise time of the enable voltage, depending on how the enable circuit is driven.

  • 0 in reply to Peter James Miller
    Prodigy 190 points

    On part 3 of your reply you state there is a 1024 master clock cycle "Soft-Start Wait" timer.  If the master clock runs at 8x the phase clock wouldn't this be 1024/8 = 128 phase clock cycles and not 256 phase clock cycles?

    Also, is there and alternate way to enable the output voltages that would eliminate this SS wait time for using the chip in a dual output configuration?  Can I hold the COMP pin low and release it?

    thanks,

    Sam

  • 0 in reply to Samuel Fritzinger
    TI__Guru 56925 points

    Sam,

     

    Thank you for the correction.  Yes, it should be 128 phase clock cycles.

     

    While holding COMP low would prevent switching, it would not prevent the charging of the TRKx pin, which would eventually charge to 1.4V and turn-on UVP, which would shut down the part due to an undervoltage event, force a time out (7 soft-start cycles) then allow a restart.  This could result in much longer delay times depending on the timing of the desired enable and the soft-start cycling.

    TRK1 and TRK2 can be forced low, which does not prevent switching, but does force the controller to attempt to regulator to near 0V (might be slightly positive or slightly negative depending on the input offsets of the error amplifier).  This would also prevent TRKx from rising to 1.4V and activating UVP.

    To ensure no switching occurs, both COMPx and TRKx would need to be forced low.

    Alternately, the enable functions have a low-voltage level threshold that enables the BP regulator (0.5 - 1.5V) if you allow the enable pins to rise above this voltage, but hold them below the UVLO threshold (1.9 - 2.1V) you can allow the BP regulator and internal oscillator to power-up without enabling the switching regulators.  This should eliminate the majority of the start-up delay time as well.