I would like to parallel two converter designs. Is this recommended? Can you answer the following questions?
1. The 1.6V offset on the EA isn't toleranced. What is the expected variation in this offset? This is one of the components in the calculation of parallel current share error.
2. I would set one transconductance EA as the master and bias the other one off. Is there any reason this wouldn't be OK?
3. Is the sync input rising or falling edge driven? I would be synchronizing the two parallel stages 180 degrees out of phase.
Thanks.