TPS65094: PMIC shutdown while low temperature testing

Hi Chentsu,

It looks like RSMRSTB is going low when V1P8A is spiking high. At 1V / division, it looks like it it's going well above the 108% power good deassertion specification, so the PMIC detects this as a power fault and restarts.

Is it happening on all boards or just one? WHat is the approximate failure rate and is it consistent? Does it follow the PMIC or the board if you swap the PMICs?

There are a few possible reasons for this type of behavior. If the MLCC capacitors have derated too heavily due to temperature and they are no longer sufficient capacitance to serve as an LC filter then the output could rise more than expected. This can be tested by adding more capacitance either by using capacitors with less low temperature derating or just adding more capacitors.

Another common problem on APL systems is the 1.8V rail being accidentally pulled up to the 3.3V rail through one of the other chips. This can occur if other ICs on the board with both 3.3V and 1.8V input have an unexpected path to allow 3.3V onto the 1.8V rail. If you scope the SW4 node at the same time as one of these events and it is not switching, then it is clear that another IC is causing the overvoltage.

If the GND connection to the PMIC is too resistive or inductive, an offset can occur. In that case, when switching, the PMIC GND goes higher than the system GND and as a result the output voltages end up higher than expected due to the mismatch. This can typically be tested by probing a GND net under the PMIC though it is not always the case.

If none of the above seem to have an impact then we can start looking into less common items.