TPS54020: question about Ratiometric and Simultaneous Startup Sequence

Hi TS,

Overall I do not see any issue with what you are planning to do but there are a few things I need to confirm.

1. Could you clarify if you plan to power 8 different 1.0 V loads or will all of the 1.0 V outputs be connected in parallel? I do not see any problem with the current configuration if you plan to have 8 independent 1.0 V outputs. If you need to parallel them, you would need something added to this to ensure proper current sharing.
2. How closely do you need the 1.0 V outputs to track each other during startup? There would be some variation in the output ramp due to circuit tolerances in the VSS to VFB offset and the ISS current.
3. Make sure you use the corrected equation suggested by John. It should be Vout2+deltaV, not Vout2*deltaV. Unfortunately sometimes these mistakes happen when the datasheet is converted into pdf and they are very easy to overlook.

Hope this helps.

Anthony

Hi Anthony,

thanks for your answer.

1.Could you clarify if you plan to power 8 different 1.0 V loads or will all of the 1.0 V outputs be connected in parallel? I do not see any problem with the current configuration if you plan to have 8 independent 1.0 V outputs. If you need to parallel them, you would need something added to this to ensure proper current sharing.

 -> Thanks for the review. 1.0V outputs are independent, there’s no need for me to use current sharing.

2. How closely do you need the 1.0 V outputs to track each other during startup? There would be some variation in the output ramp due to circuit tolerances in the VSS to VFB offset and the ISS current.

 -> How much do VSS to VFB, ISS affect on the variation in maximum?

Only thing I need is 1.0V outputs tracking 3.3V and variation among 1.0V outputs ramp-up would be less than 2.5msec.

Do you suggest 1.0V outputs tracking each other including tracking 3.3V?

3. Make sure you use the corrected equation suggested by John. It should be Vout2+deltaV, not Vout2*deltaV. Unfortunately sometimes these mistakes happen when the datasheet is converted into pdf and they are very easy to overlook.

     -> I confirmed the equation in the TI website. I have applied the correct equation which you have suggested.

thanks,

TS

Hi TS,

I apologize, I must have overlooked your question in the second item. I have two more questions with some comments before I can answer this.

Questions: How closely do you need the 1.0 V to track the 3.3 V?

Comments: When the correct equation is used (Vout2 + dV) the top resistor for the divider from the 3.3 V to the SS/TR pins is 21 kΩ. This gives an offset between the 3.3 V and 1.0 V output of nearly 0 V. When the max values for the Vssoffset and Iss from the electrical specifications table are used in this same equation, the offset becomes -0.3 V. This means the 1 V output may lead the 3.3 V output by 0.3 V. Using the min value of Iss and the typ value of Vssoffset shows that the 1 V output could lag the 3.3 V output by 0.3 V.

Question: What SS time will you use for the 3.3 V output?

Comments: As long as the startup time for the 3.3 V is in a normal range, it should not be a problem to have all 1.0 V come up within 2.5 ms. For example a 5 ms startup time could work because 2.5 ms is only 50% of the startup ramp time.

Do you actually need the outputs to track or is really only important to make sure a specific startup sequence is met? If only the sequence is important, using PWRGD of the 3.3 V output to enable the 1.0 V outputs would greatly simplify this.

Best Regards,
Anthony

Hi TS,

Zero delay is not possible with this circuit. There will always be some variation in the startup due to tolerances in the SS current and the offset from SS to FB. Some 1.0 V outputs could lead the 3.3 V and some could lag the 3.3 V.

Where does this zero delay requirement come from? Is there a maximum limit specified for the voltage difference between 1.0 V and 3.3 V?

Anthony

I double checked my calculations by coming up with an equation to estimate the 1.0 V output based on the 3.3 V output during the startup ramp. This equation is derived by simply summing the currents into and out of the SS/TR pin node. Equation is below. This equation only works for the case of Vout2 = 1.0 V. Also this equation is only valid for Vout1 up to ~1.0 V because the max voltage at Vout2 is the regulated 1.0 V.

If the 21k and 31.6k SS/TR resistors suggested earlier by John are used, then the 1.0 V output could lead or lag by ~30 mV. For example, when the 3.3 V output is at 0.1 V, the 1.0 V outputs may be 0.13 V or 0.07 V. This same offset would remain through the entire startup ramp. Will this much voltage difference be acceptable for what you are powering?

Previously I was using Equation 5 incorrectly which incorrectly suggested a larger difference.

Hi TS,

Just a couple comments.

To have the 3.3 V track the other 3.3 V rail, I suggest that you instead connect the SS/TR pins in parallel. Both parts should have a local SS/TR capacitor. The capacitance would also need to be ~2x because the two SS/TR current sources would be placed in parallel.

Will you be using the PGOOD/PWRGD outputs in your design? The output of the 1.8 V rail will not be valid because the SS/TR voltage will not reach the typical 1.2 V, 1.4 V max threshold. An external circuit work around is possible if you need this signal to be valid. Let me know if you need this in your system and I will provide a more specific suggestion.

Anthony

Hi TS,

1. Ok, got it now. I don't see any issue with this structure.
   
   
2. The reason the 1.8 V needs this extra circuit but the 1.5 V does not is the differences in the resistor divider at the SS pin.
   
   
   1. For the 1.5 V, the divider is 30.9k and 21.01k. When the 3.3 V is in regulation the voltage at the SS/TR pin is ~1.336 V. This is above the 1.2 V typical threshold so PGOOD will go high.
      
      
   2. For the 1.8 V, the divider is 35.7k and 18.909 k. When the 3.3 V is in regulation the voltage at the SS/TR pin is ~1.143 V. This is below the 1.2 V typical threshold so PGOOD will never go high.
      
      
   3. To work around this you can add an NFET which changes the SS divider for the 1.8 V based on the state of the 3.3 V PGOOD. See image below and description of how this works. This circuit assumes you have a way to invert the PGOOD of the 3.3 V rail.
      
      
   1. Rsstop remains the same.
   2. During startup, when the 3.3 V PGOOD is low, the MOSFET is on so the combination of Rssbot and Rparallel should equal the value calculated in the datasheet equations.
   3. When the 3.3 V PGOOD goes high the remaining divider should pull the SS/TRK voltage to just above 1.4 V.
   4. For the 1.8 V the two bottom resistors are calculated as:
      
      Rssbot = Rsstop*1.4V/(V1-1.4V)
      Rparallel = Rssbot*Rssbotstartup/(Rssbot-Rbotstartup)
      
      Where:
      V1 = 3.3 V rail for your application
      Rssbotstartup = the resistance calculated by the datasheet equations, 18.9 kΩ in this application.
      
      
   5. Using these two equations I calculate that you will need:
      Rssbot = 26.3 kΩ
      Rparallel = 67.3 kΩ
      
      
      
      
      

• There is no problem using a 16.5 ms soft start for the TPS54623 and you can use the equation you showed from the datasheet to select the appropriate capacitor. This is just a random limitation they decided to use in WEBENCH.

Hi TS,

What you have now looks good.