HI,
My customer has a question
Q1.When the below operating condition, I can create the project
Vin=22~26V
Vout=15V
Iout=1.5A
https://webench.ti.com/appinfo/webench/scripts/SDP.cgi?ID=5F8DECD17E67E318
Result :phase margin 75.6 deg
But,I get an error "design can not be created" when the below operating condition.
Vin=22~26V
Vout=15 -> 15.4V
Iout=1.5A
The error content is "This design is not stable due phase margin either smaller than 35 or greater than 120".
Does the phase margin change significantly by small difference in output voltage?
Best regards,
Watanabe
