TPS659037: Total capacitive load per phase

Fredda

Part Number: TPS659037
Other Parts Discussed in Thread: AM5718

Hi,

The TPS659037 Design Guide (SLIA088) section 2.2.2 states that "The total capacitive load per phase should not exceed 57μF, including decoupling capacitors at the load. Reduce the output capacitance to a minimum of 20 μF if required."

I've been looking at the AM571x Industrial Development Kit (IDK) where the TPS659037 PMIC is used together with an AM5718 Sitara MPU. Several of the SMPS outputs have loads above 100 μF. For example VSMPS3, which powers VDDS_DDR, has the following decoupling capacitors:

C278 = 47μF
C441 = 100 μF
C6 = 10 μF
and some smaller values caps...

Why isn't the Dev Kit following the recommendations? What are the consequences if any?

Regards
/F

over 8 years ago

0 Eran Shternlib over 8 years ago

TI__Intellectual 1020 points

Hello, thank you for posting your question on the TPS659037 in the e2e forum.
Your thread has been assigned to the expert within TI, who will reply to your question as soon as possible and attempt to resolve your issue.

Best regards,
Eran.

0 Karl Wallinger over 8 years ago in reply to Eran Shternlib

TI__Genius 16410 points

Hello Fredda,

We understand many processors, FPGAs, and other loads can require additional capacitance on the load. Because of this, we released an application note which shows testing at higher output capacitance on the SMPS outputs. It is ok to higher than 47uF on the outputs as long as you perform some stability testing on your board to ensure that your specific board conditions have no issues.

Our testing showed sufficient phase margin at higher capacitances, and stability was also confirmed on the AM572x and AM571x boards.

www.ti.com/.../swca286

Regards,
Karl

0 Fredda over 8 years ago in reply to Karl Wallinger

Intellectual 625 points

Thanks. That answers my question more than well!

Regards
/F

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TPS659037: Total capacitive load per phase