UCD90120A: Query on Pwr Good and setting Watchdog timer

In case of WDT I do not have a WDI pin I expect to control the WDT via I2C commands...both enabling disabling, kicking, configuring etc....

Hi Rakesh
#1. POWER_GOOD is a not a page-related status. it is a status of whole system. Please refer section 5.3 to understand the POWER_GOOD flag www.ti.com/.../slua815.pdf
if you want to monitor whether the rail has reach power good or not. please set up a TON_MAX value for the target rail, if the rail does not reach power-good at the assigned time, UCD will report a fault.
#2. the watchdog timeout can not disable/enable on the fly. you may change the reset period or delay to implmenent the need.

Regards

Yihe

Hi,

1.

My requirement was to monitor some voltage pins to determine the status of the voltage rails during the application run. These voltage rails are not part of the power ON/OFF sequence loop.These power rails are turned ON/ OFF by OPERATION command from UCD90120A and enable signals are not part of PwrON sequence. My req is not just to check the power good status once but to periodically monitor the status of those rails. So I am looking for flags which would indicate POWER FAIL/ POWER_GOOD status of said rails.

----one method could be to periodically monitor the voltage reads and compare.

From section 5.3 in doc ""at least one monitored rail does not reach its POWER_GOOD_ON threshold"" once all rails reaches power good then the signal will we asserted. Will it go low with the failure of a single rail during run time?? I this case I can monitor this bit to verify the power rail status. in case of fail i have to determine which rail has failed. For this is there any means other than individual voltage monitoring.

I presume my requirement is clear. any suggestions are welcome

2.

In case of WDT as of now I tried the following method on EVM where it seems to work as intended.Please suggest whether this is acceptable work around.

1. In the UCD image WDT is not enabled

2. In the application code I configure WDT with the following command where WDT is enabled but held in reset...

/******************************/

void_UcdWatchDogConfigure(void)

{

  /*

   * Initialize with Byte count 4,WDT disable,WSI None,Start time 3.2sec,WDt rst Period 768ms,WDO- GPIO8,

   */

   uchar luchar_data[8] = {0x04,0xD6,0x00,0x8C,0x1E};

   void_BlockWrite(SYSTEM_WATCHDOG_CONFIG,luchar_data);

}

/**********************************/

3. Release reset when desired

 

void_UcdWatchDogEnableDisable(bool lbool_EnDis)
{
    uchar luchar_data[8];
    void_BlockRead(SYSTEM_WATCHDOG_CONFIG,luchar_data);
    switch(lbool_EnDis)
    {
        case 1:
            luchar_data[1]=luchar_data[1] & 0x8F;// WDT reset release
            void_BlockWrite(SYSTEM_WATCHDOG_CONFIG,luchar_data);
           break;
        default:
            luchar_data[1]=luchar_data[1] | 0xD0;// WDT reset release
            void_BlockWrite(SYSTEM_WATCHDOG_CONFIG,luchar_data);
    }

}