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BQ25606: Input current limit

GeT
Intellectual 990 points
Part Number: BQ25606

I bought the evaluation board of BQ25606 to do some tests about chip's performance.

I noticed that when I place a very large load (about 2-3 Ohms) on the board and power on the chip with 5V (while load is already connected) input the current does not reach the expected value (3.68V / RL) but is limited to about 500mA instead.

Therefore the Vsys voltage is keepen clamped much below its typical value.

When I power up the board without connected load, and connect the board afterwards the chip is able to deliver the calculated current.

My settings is:

D+, D- floating.

RILIM = the least possible value (about 160Ohm).

CE = HIGH (Disabled)

Am I doing something wrong?

  • 0
    TI__Mastermind 25800 points

    Hey GeT,

    Is that 3.68V the measured VSYS voltage? Or is that just the value you expect? 

    Our part has an integrated soft-start function that limits the input current to 200mA until the VSYS voltage ramps up to 2.2V. 

    Regards,

    Joel H

  • 0 in reply to Joel Hernandez II
    Intellectual 990 points
    Yes if I allow the chip to power up without a large load I measure 3.68V.
    When I try to power up the chip while large load is connected then the current is limited and voltage does not reach the value of 3.68V.

    If my problem is the internal soft-start function then the maximum allowed load before voltage ramps up to 2.2V is 2.2/0.2 = 11Ohm.
    Therefore If load less than 11Ohm is connected to Vsys the chip would not power up normally. Would it?
  • 0 in reply to GeT
    TI__Mastermind 25800 points
    Hey GeT,

    Likely the soft-start is the reason for why you are seeing this.

    And technically, the load may be a little higher than that. We do not take efficiency data for start-up conditions, but assuming the power conversion in the soft-start mode is 70%, then technically the output power you can get is 5V*0.2A*0.70 = 0.7W. The minimum load on the output at that point is (2.2V)^2/0.7W = 7Ohm.

    Again, this value could be variable because the efficiency is undetermined. Will you have a purely resistive load on SYS?


    Regards,
    Joel H
  • 0 in reply to Joel Hernandez II
    Intellectual 990 points
    Ok, I do understand why that happens.
    yes my load is purely resistive made from discrete through hole resistors
  • 0 in reply to GeT
    TI__Mastermind 25800 points
    Sorry GeT,

    I meant if your load in your final application/final system will be purely resistive; not your test condition.


    Regards,
    Joel H
  • 0 in reply to Joel Hernandez II
    Intellectual 990 points

    Sorry I didn't see clearly.

    Vsys output will power a GSM/GPRS module, and some other chips and modules through LDO, such as arm mcu, GPS module digital temp sensor etc...

  • 0 in reply to GeT
    TI__Mastermind 25800 points
    And do all these devices need above 2.2V to operate as you need them to? Here I'm looking for the minimum operating voltage of all loads connected to VSYS (something like the UVLO of these devices). If they all operate above 2.2V, then the loading will not happen until after VSYS is regulated to 3.68V.


    Regards,
    Joel H
  • 0 in reply to Joel Hernandez II
    Intellectual 990 points

    All devices require at least 3.3V

    I do not care if there would be some delay before the voltage reach that UVLO (2.2V) threshold.
    I did some test in a prototype and everything worked perfect.

    My only concern was that I did something wrong on chip setup. Because when I tried to overload the chip during power up, just connecting a large resistive load before the main supply plug in, it didn't start...

  • 0 in reply to GeT
    TI__Mastermind 25800 points
    Ok, I completely understand.

    I just wanted to make sure it would work for your real application.

    Regards,
    Joel H