• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 1 answer
  • Subscribers 64 subscribers
  • Views 1115 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS53679: Layout of current sense line

Sho Ogane
Genius 5575 points
Part Number: TPS53679

Hi all.

I have one question about figure 8-3 in datasheet.
Figure 8-3. Power Stage Current sense Differential Pairs Layout Example.

You recommend paring the current sense line(VREF_P and ACSPx)

If we wire current sense line the daisy chain,  is there something problem?

Best Regards,
Sho

  • 0
    TI__Expert 4060 points
    Hi Sho,

    By daisy chaining the current sense lines do you mean connecting ASCP1 to ASCP2 to ACSP3 and so on down the line and only routing one current sense signal back to the TPS53679?

    If that's the case you absolutely cannot do that. The controller has to be able to sense each phase current individually in order to ensure proper current balancing. Each power stage is not sending back an identical signal to the controller. If only one phase is active and a large load step occurs the TPS53679 will monitor all phase current signals to know when to turn on the next phase.

    Without this information the regulator, if it even starts up, will not regulate properly.

    Thanks,

    Carmen
  • 0
    TI__Mastermind 49430 points
    Hi Sho,

    We are not sure what kind of daisy chain you are referring. But we strongly recommend routing VREF_P and CSPx as differential pair all the way from controller to power stages. This differential pair routing will give you accurate output current reading, excellent current balance and loop stability.

    Thanks,

    Nancy
  • 0 in reply to Nancy Zhang
    Genius 5575 points

    Hi Carmen san,  Nancy san

    Thank you for your support.
    I understood it.

    Sorry I have one more question.
    please tell me the following points.
    -The line width of each line(VREF_P and ACSPx)
    -The line gap between VREF_P and ACSPx

    Best Regards,
    Sho

  • 0 in reply to Sho Ogane
    Genius 5575 points

    Hi Carmen san,  Nancy san

    How about my question?

    Please give me your comment.

    please tell me the following points.
    -The line width of each line(VREF_P and ACSPx)
    -The line gap distance between VREF_P and ACSPx

    Best Regards,
    Sho

  • 0 in reply to Sho Ogane
    TI__Mastermind 49430 points

    Hi Sho,

    The width of each line is 10mils. A pair of VREF_Pand ACSPx are routed differentially with 5mils in between, and 25mils  between pairs(the closest distance).

    See below drawing.

    Thanks,

    Nancy

  • 0 in reply to Nancy Zhang
    Genius 5575 points

    Hi Nancy san

    Thank you dor your quick response.
    I understood the each line width.

    Sorry, what do you mean "closest distance"?
    Is 5mils pair best?

    >>See below drawing
    Did you attached the something picture? 

    Best Regards,
    Sho

  • 0 in reply to Sho Ogane
    TI__Mastermind 49430 points
    Hi Sho,

    I don't know why I could not attach the drawing here. The closest distance means the min. distance between pairs.
    Please email me at nancy_zhang@ti.com. I will send you the routing drawing.

    Thanks,
    Nancy
  • 0 in reply to Nancy Zhang
    Genius 5575 points

    Hi Nancy

    I would like to know the layout between TPS53679 and pair sense line(Figure 8)

    I don't know the VREF six branch point to write pair line with ACSPx.

    Please tell me the advice.
    If you have picture or file, please send me email.
    e-mail : ogane-s@clv.macnica.co.jp

    Best Regards,
    Sho

  • 0 in reply to Sho Ogane
    TI__Mastermind 49430 points

    Hi Sho,

    The VREF six branch point is in the controller side and I will send the picture in your email.

    Thanks,

    Nancy