EMB1428Q: EM1402,FET not open

menglinwang

Prodigy 100 points

Part Number: EMB1428Q

HI guys

I use EMB1428, the power part of the normal, I send command 0x10, reply 0xA1, SPI is normal, VDDCP-VSTACK is 21V.

Why the FET is not open？

ALL VGS is 0V？

thinks.

over 8 years ago

0 WM5295 over 8 years ago

TI__Guru 54715 points

Hi User,
If you look at figure 9 of the EMB1428 data sheet, notice that the fault code is being transmitted before the command is complete. Table 3 indicates "A" would be a no fault condition but with FAULT_INT set which would open all switches. An "A" code would be error "010" or secondary side current limit fault from the EM1499.
The EM1428 will be trying to exectue the command sent so if the FET switches are open from the prior command they should be closing as this command executes. Looking at the FAULT_INT signal should be helpful in understanding the mode of the part.

0 menglinwang over 8 years ago in reply to WM5295

Prodigy 100 points

HI WM5295
I did not use EMB1499,FAULT[0:3]connection GND ，DIR connection inverter to DIRRT,EN connection inverter to DONE.
FET is not turned open so EN is not pulled high.
I purpose is to separate debugging EMB1428 and EMB1499.
thinks.

0 menglinwang over 8 years ago in reply to WM5295

Prodigy 100 points

0 WM5295 over 8 years ago in reply to menglinwang

TI__Guru 54715 points

Hi User,
There could be several things going on. The part was not designed to work with an inverter between EN and DONE, that response may be unexpectedly fast for the timing, and a short EN signal might be missed by the sample rate of a logic analyzer, but I would expect you should have the FETs operate.
Check your connections and signaling. If your monitor points are on the board net test points, be sure the voltages are reaching the IC pins. Be sure all power supplies are on. I expect RST is not held in reset or you would not have data out.
The logic analyzer detail waveform does not show CS toggling while the broader view does, the datasheet shows commands ending with CS high. Note tTRANS in figure 10 and the spec table. MOSI looks much less dense than CS or MISO, I suspect most commands are for it to stop. It may be beneficial to look at the FET signals and EN with a scope during the time when CS goes high after command is sent.
Sometimes parts get broken during handling or evaluation. If you have another board you might try it. If you have only 1 it can be an ordeal to change the IC and you want to check everything else first.