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TPS54260: Need help on TPS54260DGQR Layout review

Part Number: TPS54260

Dear All,

One of my customer working on Dual USB charger based on TPS54260DGQR device and they have used 2 devices/board. 48V Input voltage to 5V, 2.5A.

Please find attached layout, please review and provide suggestions to proceed , they are unable to apply all guidelines due to lack of space and placement restrictions.

  • GND loop between IC and D1 GND path is connected at the bottom layer copper
  • VIN trace width up to VIN pin is raised to 18 mils
  • Feedback trace to R2 is taken from load side USB connector

Rgds

Aravind.DUSB.pdf

  • Please also attached the schematic of your design.

    Thank you.
  • Dear Sir/dual_charger_updated.pdfMam,

    please find attached schematics for your kind reference.

    Rgds,

    Aravind.

  • Dear All,
    please help to review and provide feedback , so we can ask customer to go for fabrication.

    Aravind.
  • There are a few comments to your layout:

    The input capacitors should be close to VIN pin and the ground pad of the diode (D1 or D3). In U1 circuit, C18, which is bypass cap for U2 is close to D1 and VIN of U1. C5 should be in C18's spot for better U1 input bypassing. C2, C3 and C4 are on the other side of the board and far from U1. They should be as close to U1 as possible. Same goes with U2 input bypass caps, they should be as close as possible.

    There seems to be only one via connecting SW node to inductor on the other side of the board. Please check the current density of one via. Is it enough for 2.5A current?

    The output capacitors seem to be 47uF in 0805 case size. What is the voltage rating on these caps? Ceramic caps derate a lot when the DC voltage on them is close to the rated voltage. For 5V output voltage, I'd recommend using 10V rated ceramic caps.

    Is this a 2-layer board or a 4-layer board? I am not sure where the output capacitor ground is connected to the IC ground and input capacitor grounds. They have a good connection, not output cap ground floating.

    Thermal vias are recommended under the DAP of the IC to help heat dissipation.

    Please refer to layout recommendations on page 41 of the datasheet

    www.ti.com/.../tps54260.pdf