This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM5023: LM5023 Startup

Part Number: LM5023
Other Parts Discussed in Thread: LMV431

Hi

This posting is a sequel of "Multi output Flayback design".
We modified LM5023EVM and try to confirm working.
However, the device does not do a startup.
This is waveform of VCC(green) and VSD(blue).tek00002.tif

And the remodeling points are as follows.
EVM_modify.pdf

It did not work even if I raised the input voltage (+V=DC 0V->50V).
Is there the point to modify elsewhere?

Best Regards,
PAN-M

  • Pan,

    What happens when you apply the input voltage? Is there any switching at the OUT pin to drive the MOSFET?

    Does Vout start to rise? Can you post detailed waveforms?

    One issue I can see with the modifications is that the LMV431/opto may not be able to regulate the 3.3-V rail properly because R20 value is too big. LMV431 needs min 1.24 V at cathode. allow 1.2 V for opto Vf drop. That leaves ~0.86 V max across R20. The opto CTR is 100% min, and Icomp ~150 uA, so R20 < 0.86/0.15 mA = 5.6 k max.


    Thanks,
    Bernard
  • Thank you for comment.

    When I apply the input voltage, it becomes the saw wave pattern from a beginning.
    And it does not happen the output of VOUT and the switching of OUT.
    (I was triggered OUT waveform.)
    And also SS pin is low.

    Regards,
    PAN-M

  • Pan

    Can you also check the voltage waveforms at the SS & COMP pins?

    Something must be causing them to remain low and prevent any PWM activity.

    Thanks,
    Bernard
  • Bernard

    Thank you for support.
    Our customer gave up this specifications because there was not time.

    Probably neither SS nor COMP worked.
    I think that OUT and SS should begin start when VCC reached to 12.5V to be shown in figure 17, but do not work.
    What kind of state is the initial value in COMP?

    Regards,
    PAN-M

  • Pan

    At startup, SS will be low, close to GND. When VCC reaches the start threshold, VSD goes low to turn off the external startup FET. At the same time, the internal current source will charge the external SS cap, so SS will ramp linearly. COMP will be clamped close to the SS level, so it will also rise linearly.

    When COMP exceeds ~0.5 V (the internal COMP to CS offset represented by the diode in the block diagram), then the PWM comparator will start to allow PWM pulses at the OUT pin.


    It would be useful if the customer can check the SS, COMP & CS pins.

    Maybe the track cut on the SS pin was not done correctly, and if SS is held low, this will prevent startup.


    Thanks,
    Bernard
  • Bernard

    I am checking a transformer using by different circuit, but as for this transformer, polarity seems to be reverse to a drawing.
    If the polarity of the transformer is reverse, does it make such a move?

    Regards,
    PAN-M

  • Pan,

    Yes, reversed transformer polarity would cause an issue - the OUT pin would probably turn on briefly for just 1 cycle, then the current at the CS pin would rise rapidly, trip the OC protection, and cause the IC to shutdown and retry when VCC has decreased and recharged to the start level.


    Thanks,
    Bernard