Hi,
There is power-up sequence waveform in DS Fig.33 and the EN goes to High after VREG reaches 5V. However EN pin is applied from VDD at EVM and so EN goes up before EN reaches 5V as attached.
Then please let me know if there is no start-up issue when EN connected to VDD directly or voltage divider?
Best Regards,
Satoshi / Japan Disty
