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UCC28950: Several questions for SYNC terminal.

Part Number: UCC28950

 Hello guys,

 One of my customers is designing a schematic for their product uses UCC28950. They have several questions about SYNC terminal as the follows. Could you please give me your answer or comment to the questions?

 Q1.  What is the SYNC terminal maximum driving current when the terminal works with output mode?

 Q2. What is the threshold voltage when the terminal works with input mode?

 Q3. What is the maximum voltage which can applied to SYNC? Is it 5V?

 Q4. What is the minimum voltage which can applied to SYNC? Is it 0V?

 Your reply would be much appreciated.

 Best regards,

 Kazuya Nakai.

  • Q1. What is the SYNC terminal maximum driving current when the terminal works with output mode?
    The SYNC output is a digital line so it should be buffered if driving an external circuit. The exception to this is that two or three SYNC pins may be driven directly as inputs (slave devices) from a single SYNC output (master device)

    Q2. What is the threshold voltage when the terminal works with input mode?
    I don't understand this question -

    Q3. What is the maximum voltage which can applied to SYNC? Is it 5V?
    It is Vref+0.4V (or 5.4V)

    Q4. What is the minimum voltage which can applied to SYNC? Is it 0V?
    it is -0.4V

    regards
    Colin
  • Hello Colin,

    Thank you very much for your prompt reply.

    About Q2, I think that SYNC terminal is input mode when UCC28950 is slave mode.
    At that case, our customer wants to know what the SYNC voltage recognized as LOW level. Is it less than 0.8V (TTL level)? Or less than 30% of VREF (CMOS level)? Also what is the SYNC voltage recognized as HIGH level? Is it greater than 2.0V (TTL level) or 70% of VREF (CMOS level)?

    Your answer would be much appreciated.

    Thank you very much again and best regards,
    Kazuya Nakai.
  • Hello Colin,

    Could you please give me your reply?

    Thank you and best regards,
    Kazuya Nakai.
  • Hello Nakai-san

    I have asked the design department for the details on the SYNC pin levels - I'll post their reply when I get it.

    You are correct, the SYNC pin is an input when the device is in slave mode. Also - please note that when the UCC28950 device is disabled (SS/EN pulled below VSS_STD, 0.5V nom), while powered on, it will actively try to pull the SYNC pin low with its output stage (not just a weak pulldown.)  This stage has a series 200Ω (nominal) between its output and the SYNC pin.

    Regards
    Colin

  • Hello Colin,

    Thank you very much for your reply and I noted that the SYNC pin is pulled down to GND with about 200 ohm when SS/EN pin is low level.
    I see. I will wait the reply from your design department person.

    Thank you and best regards,
    Kazuya Nakai.
  • Hello Colin,

    Did you get any data?

    Thank you and best regards,
    Kazuya Nakai.
  • Hello Nakai-san

    No, I have not yet received a reply, I've sent them a reminder today but they are busy people and getting to the top of he queue takes time.

    I'll post their reply when I get it but please do remind me if we don't get back to you in the next twwo weeks or so.

    Regards

    Colin

  • Hi Colin,

    I see. I will remind you after two weeks when that case.

    Thank you and best regards,
    Kazuya Nakai.
  • Hi Nakai-san

    Excellent - Thanks

    Regards
    Colin
  • Hi Colin,

    The customer needs to know the information as soon as posible. Could you please tell me the information?

    Thank you and best regards,
    Kazuya Nakai
  • Hello Nakai-san

    I got the following information from the design department this morning - N is 5.

    Please let me know if you need any further information.


    Regards

    Colin

    Measurement

    Corner #

    Minimum

    Maximum

    Mean

    Std-dev (SD)

    Mean-N*SD

    Mean+N*SD

    VIH

    -40C

    2.14E+0

    2.29E+0

    2.21E+0

    31.9E-3

    2.05E+0

    2.36E+0

    125C

    2.20E+0

    2.36E+0

    2.27E+0

    34.9E-3

    2.10E+0

    2.45E+0

    VIL

    -40C

    2.09E+0

    2.25E+0

    2.17E+0

    33.3E-3

    2.00E+0

    2.33E+0

    125C

    2.15E+0

    2.32E+0

    2.23E+0

    36.8E-3

    2.04E+0

    2.41E+0

    hyst

    -40C

    33.2E-3

    42.5E-3

    39.0E-3

    2.0E-3

    29.2E-3

    48.8E-3

    125C

    40.1E-3

    52.5E-3

    47.4E-3

    2.6E-3

    34.5E-3

    60.2E-3

  • Hello Nakai-san

    I also got the following summary information on the behaviour / characteristics of the SYNC pin -

    Rin = 300k ~ 1,000k
    Cin = ~2pF
    VIH = 2.13 ~ 2.35
    Hysteresis = 35 ~ 55mV


    Regards
    Colin
  • Hello Colin,

    Thank you very much for the clear information. I appreciate your effort to get it.

    By the way, could I ask you a few questions for the information?

    1. What was VDD voltage when the data was taken? Was it 12V?

    2. Is the data not changed depends on VDD voltage? (Does the input buffer of SYNC operate with 5V generated by a internal LDO?)

    3. What is the maximum input low level voltage and the minimum high level voltage TI recommends? (For example, the maximum input low level voltage = 30% of 5V. the minimum high level voltage = 70% of 5V).

    Thank you very much again and best regards,
    Kazuya Nakai.
  • Hi Nakai-san

    1/ The values don't depend on VDD - typically Vdd is 12V.

    2/ levels are not dependent on VDD. SYNC operates off an internal 5V rail. Please note that the Abs Max rating on the SYNC pin is VREF + 0.4V

    3/ The 5 sigma levels are VIL = 2.06V so that any voltage less than 2.06V will be treated as a LO level. VIH is 2.37V so any voltage greater than 2.37V is treated as a HI level. Your example levels, 30% and 70% of 5V would work well.

    Regards
    Colin
  • Hi Colin,

    Thank you very much for the kind support of you and your team.
    The data and your reply are very helpful.

    Thank you again and best regards,
    Kazuya Nakai.