I would like to use an LMZ30606 to power an FPGA. Once the FPGA is configured, it will supply an external clock signal to synchronize the LMZ30606. If the FPGA is reconfigured (which is not typical, but not uncommon for this application - firmware upgrade, for example), the FPGA's external clock signal will stop and resume once configuration is complete. The LMZ30606 datasheet states "It is not recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to a lower frequency before returning to the switching frequency set by the RT resistor." What frequency, and for how long - what are the consequences?
Are there any recommendations for using the LMZ30606 in this manner, or is this simply the wrong part for this application?
