TPS65251: problem with Start-up time

KIM Andy

Part Number: TPS65251

Hello

The customer has a problem with the start-up time of the design with the TPS65251.

At present, 8.3ms for 1CH, 10.1ms for 2CH, and 24.1ms for 3CH, the startup time is too long.

Green : Ven, Yellow : Vout

Can we improve this?

<<schematic.pdf removed[LE]>>

over 7 years ago

0 Vental Mao over 7 years ago

TI__Expert 5745 points

What's the things connect the DUT_1P8_EN? For the BUCK, if the EN enable, the Vout will start up quickly, don't have such a delay.

Do you measure the Ven signal in the EN pin of IC?

0 KIM Andy over 7 years ago in reply to Vental Mao

Expert 2530 points

HI
The FPGA (CPLD) supplies voltage signals to each ENABLE.
The problem is that the output is delayed even if a signal is applied to ENABLE as shown in the waveform above.

0 Vental Mao over 7 years ago in reply to KIM Andy

TI__Expert 5745 points

i see, please disconnect the CPLD and use a pulse to see if the delay still have.
I suppose the CPLD introduce the delay

0 Zhao Ma over 7 years ago

TI__Genius 15135 points

Hi, Andy

1. The CH1 and CH2 is normal, they cannot be shorten.

2. The CH3 looks abnormal.

please check:

a, Does CH3 have long startup time in every board?

b, Disable CH1 and CH2, then enable CH3 alone, please check the startup time again.

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TPS65251: problem with Start-up time