LP8863-Q1: LP8863-Q1 power supply

Hi,

Please refer to Fig 28 on datasheet for power sequence.

VDDIO can be connected to LDO output, and LDO can be enabled when VDD rises higher than POR level.

CPUMP is output of charge pump when internal charge pump is enabled(by default), and can be also input for gate drive power of external SW FET and should be connected to higher than 5V.

There is no specific requirement between VDD and VDDIO timing as long as EN comes later. Vin should be also earlier than EN too.

Hope this helps,

Hello Sung-san

Thank you for quick response.
I have one more question.
Please tell me the power supply rail necessary to operate the DISCHARGE circuit?

Regards
Tomohiro Nagasawa

Hi Nagasawa-san,

Do you mean DISCHARGE function of LP8863-Q1?
It's not necessary to use this function if you don't want. This pin can be floating if not use.
But this will help fast boost discharge during shutdown and potentially prevents any side effects by high voltage during power off.
Thanks,

Hi Nagasawa-san,

Input power rail won't need any discharge function for LP8863 because Vin will be disconnected by PL FET control when EN goes low, and other power rails won't affect boost operation. Please make sure EN signal's transition time is fast enough like other digital signals.

Hope this helps,