TPS65910: PWRHOLD pin of TPS65910

HI Masami,

The PWRHOLD signal is level sensitive, not edge sensitive, so being high prior to VSYS > UVLO should not be an issue. I tested about 20 times and didn't see an issue.

Figure 6-1 shows the POWER ON enable logic, that may provide more information on what is happening; the gating items for a POWER ON include PWRON long key press and thermal shutdown. DEV_OFF bits shouldn't apply since they would be reset.

Also note that if the VRTC does not reach it's target of 1.8V, then the OTP will never load and device will be stuck between NO SUPPLY and OFF state.

Hi, Kevin-san,

Thank you for your reply.
The difference between the previous circuit diagram and the customer's circuit diagram is that PWRON is set to Open and the primary battery is connected to the VBACKUP pin.
In other words, 1.8V is always outputted to VRTC, and ON/OFF of power supply is done by supplying 5V to VBAT or not.
A phenomenon occurs in which power supply other than VRTC is not output once every 10 times, but which signal other than the PWERHOLD signal affects this phenomenon?
OSC32KOUT and VREF are output normally even when a phenomenon occurs.
SLEEP remains at 0V.
Please give me advice.

Thanks, Masami M.

Hi Masami,

Does toggling the PWRHOLD pin voltage during one of these failed boot scenarios cause the device to start?

This thread seems to have some similar issues and they appear to have used an RC on the PWRON pin to create a start-up; but I'm not sure if they have the PWRHOLD connected properly or not:

 

Hi, Kevin-san,

Thank you for your support.
I asked the customer to check whether to start by toggling the PWRHOLD pin.
However, it seems that the occurrence is getting smaller, please wait for a while.

Thanks, Masami M.

Hi, Kevin-san,

Thank you for your support.
We got confirmation result from customer.
Power was turned on normally as a result of turning on / off only the PWRHOLD pin from the state where the phenomenon occurred.

Thanks, Masami M.

HI Masami,

I'm still not seeing any issue on my side. I've tested PWRHOLD supplied before VCC7 (or any VCC for that matter) and no matter what the part seems to boot. For example, here is 1.8V PWRHOLD and 5V VCC:

I also tried 3.3V and 5V on PWRHOLD, as well as 4 V and 2.6 - 3 V on VCC in a slow ramp.

Can you reproduce the issue on an EVM? It may be system specific. 

One other item would be does the VRTC reach 1.8V in the case where it fails to boot? If it gets stuck at even 1.65 V, the OTP would not load and the part would not boot.

Hi, Kevin-san,

We do not have TPS65910EVM.

The voltage of VRTC is always 1.8V.

Since the primary battery is connected to the VBACKUP pin, the voltage does not drop from 1.8V.

Also, the output of VRTC pin is only connected to BOOT1 except the capacitor.

To the RTC power supply (VDDS_RTC) of the processor, 1.8V is supplied from +5V of the external power supply through the LDO.

Therefore, PWRHOLD goes High (1.8V) when the +5V power supply rises to about 2.8V.

I tried adjusting the LDO's rising edge using the EN pin of the LDO to adjust the +5V power supply to about +4V and PWRHOLD to be High(1.8V), but a phenomenon that did not start up occurred.

In addition, although POWON Pin is made open, they connected a resistance(510k) and a capacitor(10u) to that pin, but a phenomenon which did not start up occurred.

Thanks, Masami M.

Hi Masami,

The TPS65910AEVM-583 is available on the web for debugging purposes.

Is this happening on all boards or just one? If just one, have they tried doing an ABA swap? I.E. putting suspected bad PMIC from bad board on a known good board and putting the known good PMIC from the good board onto the suspected bad board. This may help to identify if the board itself is the problem or if there is a board - PMIC interaction.

Hi, Kevin-san,

Only one case is surely confirmed by customers. But there are other suspicious phenomena in the market.
As for the exchange, we discuss with the customer but it is difficult because it occurs less frequently.

Please check the points again.

a.

About sampling of PWRHOLD, it is described in the data sheet as follows.

----------
6.3.3.2 PWRHOLD
When none of the devices power-on disable conditions are met, a rising edge of this signal causes an OFFto-
ACTIVE state transition a transition back to OFF state.
----------
However, this is good with understanding that sampling by level is wrong.

b.
There was an example that solved by connecting a resistor / capacitor to PWRON although we told another thread.
However, since the customer's circuit drives PWRHOLD to 1.8V using a separate power supply, I think PWRON should remain OPEN.
Is this correct?

Thanks, Masami M.

Hi Masami,

I have confirmed that the PWRHOLD pin is level dependent. A rising edge causes OFF-to-ACTIVE transition because device will detect the high level, not the edge. Experiments in the lab confirm this.

PWRON should remain high, which should be achieved in this case with OPEN due to the pull-up enabled by default. 

Hi, Kevin-san,

Thank you for your answer.
I will inform the customer about that information.

Thanks, Masami M.