Referring to the datasheet, the PG output description states that the Vds rising and falling are subject to a 9msec timer, whereas the UVLO sets PG low immediately. The functional block diagram shows EN, POR and PG combined logically to produce an internal Enable signal; does the PG react directly to the combined logical signal or just the UVLO comparator output? That direct relationship to UVLO is not depicted and there is an implication in the diagram that EN would have the same immediate effect as UVLO.
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