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TPS28225: Shoot through protection

Guru 16770 points
Part Number: TPS28225

Hi

TPS28225 has shoot through protection block internally.

1.

What is the effect of shoot through protection? 

What is the difference from dead time control?

2.

We are considering gate resistor between driver and gate of FET to improve switching noise.

If large gate resistance is selected (e.g. 100ohm, 1Kohm), what is impact caused?

Could you please give me your expertise?

BestRegards

  • Hello na na 78,
    I am an application engineer with TI and will work to answer your questions.
    The effect of shoot through protection is to ensure that the gate drive signal from one output, UGATE for example, is confirmed to be low before the other output is enabled to go high. The TPS28225 has adaptive shoot through protection which results in a low value dead time, 14ns typical, between the UGATE and LGATE switching transitions.
    The shoot through protection does provide a dead time between transitions, so in one respect this is a minimum dead time control. Dead time control in general in many cases results in a larger value dead time than the minimum required to prevent cross conduction.
    Since the TPS28225 shoot through protection logic uses the state of the driver outputs to control the minimum dead time, the concern of large value gate resistors is that the driver output could be detected as low, while the MOSFET gate to source is still high. It is possible large values of gate resistance may result in some MOSFET VGS overlap conditions.
    I would confirm the MOSFET VGS signals and switch node with the desired gate resistance.

    Regards,
    Richard Herring
  • Hi na na 78,

    I work with Richard Herring and to follow on his post -

    App note on predictive (adaptive) gate drive - this is not the same approach as TPS28225 adaptive deadtime but will help with concept understanding.

    The current, charging and discharging the gate, is limited by the gate resistor Rg. Therefore its best to start here for a minimum gate resistance with this respect. This charging/discharging current must be lower than the peak current allowed for the driver IC’s output stage to guarantee the safe operation.

    The gate resistor will limit The value of your peak current (charging/discharging) with I=V/R
    where V= VCC-VEE
    and R = Rds_on/off + R_gate_charging/discharging

    Optimizing Rg for noise is a trade-off:
    The changing of the gate resistance will influence (among other things) the switching speed of the power device, which will have an impact on efficiency and noise. Higher gate resistance values can be beneficial from the driver IC’s loss-situation and thermal point of view. What needs to be considered when reducing the value of the gate resistor is the di/dt generated when high currents are switched too fast. Its a tradeoff between increased switching losses and thermal performance vs decreased switching loss and added noise.

    Decreasing the gate resistance too much leads to increasing peak gate current - the turn-on and turn-off time will be shorter and the switching losses will be reduced. In contrast, when a lower gate resistance is applied, the switching will become faster which can reduce the switching loss. Meanwhile, the noise induced by di/dt and dv/dt will increase with higher switching speed.

    What FETs are you using?
    whats your FSW?
    Whats your VCC and VEE?

    Thanks,

  • Hi Richard, Jeff

    Thank you for your advice in detail.
    I understood a risk of large gate resistance for dead time control.

    Commonly, what kind of method is good at improvement of switching noise for gate driver such as TPS28225?

    BestRegards
  • Hi nana78,

    Thanks for the great follow up question, sorry for the late reply as well.

    Check out this app note on reducing switch node ringing.
    www.ti.com/.../slpa010.pdf

    To reduce noise for a gate driver the most important thing to first do is maintain careful PCB layout to minimize the parasitic loop inductance in circuit. The best way to reduce noise is to know where the noise is coming from. Most commoningly high di/dt and dv/dt with in the gate drive high side loop need a gate resistor to slow turn on down and prevent the hard switching affect of the HSFET which limits the di/dt and dv/dt seen on the switch node.

    When using TPS28225 gate driver (which is very fast) there are a few design procedures to follow within the DS. The DS (8.2.2 Detailed Design Procedure) recommends to use a bootstrap resistor and a snubber and output component selection for optimizing response and thermal performance. There are also layout guidelines that tell you to locate driver physically close to the power switch which will end up reducing power dissipation and thermal stress in controllers by moving gate charge power losses from the controller into the driver.

    Thanks,
  • Hi Jeffrey

    Thank you for your information.
    I'll follow these recommendations.

    BestRegards
  • Hi nana78,

    Sounds good, thanks for following up. I assume and hope that I fully answered your question. If the answer is to your liking please "verify answer". I will close this thread as such, however feel free to make a new thread if any more questions or comments pop up.

    Thanks,