• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 1535 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS767D3: TPS767D318 RESET QUESTION during POWER DOWN

Iven Xu
Intellectual 2090 points
Part Number: TPS767D3

Hi LDO expert,

I meet a question about TPS767D318, you can see below schematic, which customer made a mistake - connected the res1.8V to DVCC_3.3.

customer understand this is not the correct design and they will modify in the next version design.

But based on this design, we found an interesting test result about the res_1.8 and you can find the test waveform as below.

test condition:

When vin 5V start to power down, then monitor the DVCC3.3 and res_3.3 and DVCC1.8 and res_1.8.

We can see from the test waveform the DVCC3.3 going down firstly and when the DVCC3.3 below 3.16V, then the res_3.3 going to logic "LOW".

Also, you can see the res_1.8 going down follow with DVCC3.3 (this is make sense becuase the res_1.8 been pulled up to DVCC3.3) before DVCC1.8 start to going down.

But, you can see the res_1.8 then going to logic "LOW" before the DVCC1.8 start to going down. could you please help comments on this test result? why?


Best Regards

IVEN XU

  • 0
    TI__Mastermind 23361 points
    Hi Iven,

    Once you have 5V vin power down, the internal circuits to control the logics may also be shutdown. Once Vin has been removed, the logics have entering non-defined regions and those behaviors are not specified.

    Regards,
    Jason
  • 0 in reply to Jason Song
    TI__Intellectual 2090 points

    HI Jason,

    thanks for your feedback, so based on your comments.

    but why the 3.3V rest internal control logic looks work normal based on the test resutl, and I have checked the block diagram of this part.

    We can see before 1.8V start to power down, which means the internal LDO work for this channel and you can see the reset control logic circuit is also be powered from the same Vin, so my understanding is when the Vin start to power down, and it looks the 3.3.V output first to power down and reset 3.3 logic still work at this time (becuse maybe the Vin is not down to very low and the control logic still work for 3.3V channel).

    At this time the 1.8V still work and it looks the reset 1.8V logic still work (based on our test result), then the Vin still keep down( maybe down to some value) then the loigc 1.8V be shut down (but you can see from our test result, when the reset 1.8 start to go down to logic "Low", the 1.8V LDO still work, so I cannot understand why the 1.8V logic be shunt down and 1.8V LDO still work?)

    maybe need your help to check with designer, thanks.

    Meanwhile, can you please help check the page 3 RESET minimum input for valid reset?

    Best Regards

    Iven Xu

  • 0 in reply to Iven Xu
    TI__Mastermind 23361 points
    Hi Iven,

    Will you be able to provide screenshot with the behaviors of your 5V vin? For the "minimum input voltage for valid /RESET", it's a typical value only, let me check to see if we have any data collected over temp.

    At the mean time, will you also help me to understand why it's important for them to have the right logic while Vin is already off?

    Regards,
    Jason Song
  • 0 in reply to Jason Song
    TI__Intellectual 2090 points

    Hi Jason,

    1, I am sorry I cannot do the further test currently.

    2, they do not need to have the right logic while Win is already off, and customer need the reset logic work while Vout_3.3 or 1.8V drop down to some value.

    So if Vin starting to drop down and drop down to some value, then the Vout_3.3 or 1.8V should be started to drop, so customer think the reset logic should work when 3.3V or 1.8V output drop down to some value, right?

    Best Regards

    Iven Xu

  • 0 in reply to Iven Xu
    TI__Mastermind 23361 points

    Hi Iven,

    I got your point. Based on the screenshot you provided, when the 1.8V Vin is still there, usually /RST signal of the 1.8V output should not drop if the Vin of the 1.8V output is still beyond the minimum Vin for the RST logic. But without having the behaviors of the two inputs of the LDO on the same plot, it's hard for us to know what caused this unusually behavior of the /RST pin. 

    Regards, 
    Jason Song

  • 0 in reply to Jason Song
    TI__Mastermind 23361 points
    Hi Iven,

    Considering the 200ms delay on the /RST pin, when you take new screenshot, can you include no less than 200ms on the plot after the drop of the /RST signal? That would definitely help us.

    Regards,
    Jason Song