• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 63 subscribers
  • Views 1175 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM3488Q-Q1: Require inputs for Major Component placement in SEPIC mode

Dhvanish Parekh
Prodigy 90 points
Part Number: LM3488Q-Q1
Other Parts Discussed in Thread: LM3488

Hi Team,

We are working in one battery powered project, where device will take power input from Vehicle battery (Vin = 8 ~ 16V) and require 12Vdc as output. For such kind of buck-boost configuration we have used LM3488Q-Q1 IC in design.

Below I have pasted image of schematic design. Kindly review.


 

We have gone through the layout guideline provided in datasheet, but it has described point when application is in Boost mode. Taking that as reference we tried to make current loop from L4-Q6-D4 as small as possible. Above that below are some point where we require your inputs:

1. Is there any special requirement in placement of L3? Do we need to consider loop involving L3 for AC noise reduction?

2. In reference layout, they have tried to make GND shape common on top side for IC & its associated by providing vias for DR (pin#6) pin & VIN (pin#8) pin connection with its discretes.
 Is it OK to have vias for such switching nodes & power inputs?

3. Any other recommendations, which we need to take care during placement & layout?


Below added image of component placement done for LM3488 IC:

Let me know if require any further detail for review.

Thanks,

Dhvanish Parekh

  • 0
    TI__Mastermind 21720 points
    Hi Dhvanish,

    Schematically the circuit looks good. Please just ensure that the MOSFET and the inductors can handle the maximum amount of current.

    Please see my comments below on the layout.

    1. Is there any special requirement in placement of L3? Do we need to consider loop involving L3 for AC noise reduction?

    As with any converter the current loops of the power path need to be minimized. The switch node size should also be minimized. The above layout does and okay job of this.

    2. In reference layout, they have tried to make GND shape common on top side for IC & its associated by providing vias for DR (pin#6) pin & VIN (pin#8) pin connection with its discretes.

    Is it OK to have vias for such switching nodes & power input
    It is okay to put Vias in the GND plan. This allows for the GND of the entire board to be connected together. Using vias for pin such as VIN and DR allow for better routing, which can help reduce noise on signals.

    3. Any other recommendations, which we need to take care during placement & layout?

    This article talks about some of the generic guideline for layout of a SEPIC converter.
    www.eetimes.com/author.asp

    Please let me know if you have any questions.

    Thanks,

    Garrett