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TPS2490: How close to 0V Vcc is PG guaranteed held low?

Rick Hille
Intellectual 410 points
Part Number: TPS2490

I'm looking at approaches for a latching ON-button EN drive circuit, which might work using the PG output as long as it's guaranteed in internal design to be pulled low from 0V up to the UVLO threshold.  The description states that UVLO operates immediately without the delay path, but no indication how close to 0V PG is valid.  I suspect I won't be able to depend on this output but it's good to know at what input voltage it starts/stops becoming active for applications where it is fed to downstream circuitry that is run from a different power source.

  • 0
    TI__Expert 5940 points

    Hi Rick,

    This is specified in the EC table of the TPS2490 DS.  It depends on the sink current you are applying.  At 4mA, the max spec = 0.5v.

    Brian

  • 0 in reply to Brian Daugherty
    Intellectual 410 points
    Sorry, I was not looking for the DC characteristics of the PG output. Let me explain my question: when the device is powered up and input voltage to the device falls below the UVLO level, internal logic pulls PG low immediately. How close to 0V can Vcc fall before the internal circuitry can no longer keep the internal pulldown active? The same applies on Vcc rising. On the assumption that the current it is sinking is 1mA or less, is the PG signal internally treated to guarantee that it is sinking current actively (not leakage) during input power ramps in either direction in the region of 0V through UVLO?
  • 0 in reply to Rick Hille
    TI__Expert 5940 points
    Rick,

    That isn't characterized as a POR on the DS so you will have to assume that the Vcc UVLO is the defining item. The upper edge of that is 8.4 nominal, 8.8v max with a falling of 8.3v nominal, 7.5v min. Treat it as a POR. However, it is possible that an internal separate POR is present that will allow a lower Vin point - but don't count on this.

    Brian
  • 0 in reply to Brian Daugherty
    Intellectual 410 points
    Presumably, to support the application suggested in SLUA362, the UVLO POR mechanism must guarantee the main MOSFET Gate drive pin remains at or below the OUT pin voltage. It would have made sense to extend that to the PG output, but since it's an open-drain, the only option is to pull it up to the output directly or to a rail derived from the output. That, unfortunately, adds a messy complication since any substantial load-side capacitance would either need to be actively discharged once the UVLO threshold is crossed, or the output, feeding the PG pullup, would need to be disconnected from load capacitance by diode or a second MOSFET.