• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 63 subscribers
  • Views 341 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS54550 Sync Oscillations

Samuel Fritzinger
Prodigy 190 points
Other Parts Discussed in Thread: TPS54550

I am testing a TPS54550 3.3v design and getting some low frequency oscillations on the output when I sync the supply with a funciton generator.   I notice that if the sync frequency is very close the the free-running frequency then I get no oscillations, but if I vary the sync frequency about 1% high or 0.3% low then I see the oscillations in excess of about 50mVp-p.  I tested my breadboard and an eval board and got similar results. 

-Do you have any suggestions on what this might be and how to get get rid of it?

Also, the datasheet says to set the free-running frequency to +/-10% of the sync frequency.  If the RT frequency varies +/-15%, as shown on the datasheet with a 1% resistor, then this can't be met unless a 0.1% resistor will get a better tolerance than +/-15%.

-What would be the tolerance of the free-running frequency with a resistor that has a different tolerance?

thanks,

Sam Fritzinger

  • 0
    TI__Guru**** 191445 points

    We do not know what could cause that.  So far as we know, there should not be that type of interaction.  I plan to research this further but it will not be for at least another week or so.  If I find anything useful I will post.

  • 0 in reply to JohnTucker
    Prodigy 190 points

    John,

    Have you had a chance to look at this problem? 

    thanks,

    Sam

  • 0 in reply to Samuel Fritzinger
    TI__Guru**** 191445 points

    The IC designer is out of the office.  From our previous investigations:

    I got the designer to re-look at this.  He admits that both internal and external osillators are running cincurently, so beat frequencies are possible. 

    The observed low frequency ripple on teh output occurs at the difference frequency between the two oscillators and increases as the differences increases towards the bandwidth of the closed loop.  It difference frequencies above the closed loop crossover frequency, the ripple voltage is attenuated

    I had originally recommended operating with the external SYNC frequency intentionally above or below the RTset frequency to allow the converter bandwith to attenuate the ripple, even though the datasheet recommends +/- 10 % difference maximum.  As it turns out there is a reason for that limitation.  The TPS5454x50 does not use a true PLL circuit, but rather a scheme similar to the older low voltage devices such as the TPS54610.  Whether the frequency is controleled by teh RT clock or SYNC, the PWM ramp is charged at the RT rate.  The SYNC clock either terminates the ramp charge prematurely (higher frequency) or allows  the switching period to extend with the PWM ramp railed out at the peak value (no longer a sawtooth wave form).

    So there are consequences to operating at sync frequencies very far from the RT set frequency.  When the SYNC freq. is higher than the RT freq., the modulator gain is suppressed.  When the SYNC freq. is lower than the RT freq., the maximum duty cycle is reduced.  It would be best to insure that the SYNC frequency is as close as possible to RT for best performance.  You may be able to get by with SYNC much lower than RT if you are deigning a low duty cycle (Vout much less than Vin) converter.

    So I guess I would recommend to set teh sync clock far enough away that the ripple is reduced enough for your application.  I will ask about a work araound when the IC designer returns.