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TPS54394: Power good connection problem

Will Wang47
Expert 5470 points
Part Number: TPS54394

Hi team,

I have one question about the Power Good connection of TPS54394.

In our EVM, PG1, PG2 are pulled up through 100k resistor to VREG. I think this is because the PG1,PG2 max voltage is 5.7V.  Is that right?

If my input voltage is 5.5V, can I pull up PG1, PG2 through 100k resistor to Vin(5.5V) directly?  

Thanks,

Will

  • 0
    TI__Expert 5745 points
    If your Vin can be less than 5.7V, you can connect the PG to the Vin with 100K resistor
  • 0 in reply to Vental Mao
    TI__Expert 5470 points

    Hi Vental,

    Thanks for reply. And I did a experiment use our tps54394 EVM, just as you say, I connect PG to Vin with 100k resistor. Get the below waveform.

    1: Vin; 2:Vout2; 3:VREG; 4:PG2.

    PG2 is a small spike, so could you tell me why their is a spike? And if I change the pull up resistor, the spike could be higher? For if customer wants to use PG to achieve power-on sequence control, the spike level must be considered.

  • 0 in reply to Will Wang47
    TI__Expert 5745 points
    Pls upload your schematic.
    Try connect the PG1 to the VREG and Vout to the waveform. Is there still have the spike?
  • 0 in reply to Vental Mao
    TI__Expert 5470 points

    I use the EVM for test, and PG1 is connected to VREG. There is no spike.

    However the customer connect PG1 to Vin, and max Vin is 5.5V. So there is a spike in PG1. They want to know why there is a spike? And if the pull up resistor will influence the spike amplitude.

  • 0 in reply to Will Wang47
    TI__Expert 4875 points

    HI Will,

    Before Vin higher than around UVLO, the device is not wake up and internal power is not ready. The PG FET will be high impedance so you will see the spike. On contrary, If PG is pulled up to VREG5 or Vout, the spike is not there since the device will not have Vout or VREG5 before UVLO. The spike amplitude will depend on Vin amplitude before UVLO. Hope it will answer your question.