BQ76200: Discharge/Charge MOSFET placement

Hello

WM5295 said:

CHG_EN is grounded, it should be controlled.

Sorry, was a fault. C_ON should be connected to CHG_EN, not CP_EN.

WM5295 said:

R1 appears to be a leakage path.

Let's just ignore it, its a remainder from earlier circuits.

WM5295 said:

It may be possible to design a circuit for Q3 controlled by CHG to provide level shifting and gate control.

Isn't that the sense of the BQ76200?

WM5295 said:

In general the configuration shown will not work since the CHG pin swings between VDDCP and BAT potentials. When you want the DISCHARGE off the CHG pin will hold approximately the BAT+ voltage at R5 which will leak to the DISCHARGE output. Depending on your voltage the Q3 FET could be at risk and the charge pump could be overloaded by R5.

Is there any difference between the CHG and DSG output? If not, why isn't this a problem when there is no Q3/R5 or if they are to the left of Q1/Q2 as in the datasheet? Can this be resolved by switching DSG with CHG? In the datasheet, there is always a 10M resistor at the Gate-Source of the FETs, so why should this overload the charge pump? Assuming 40V BAT and 50V VDDCP, a 470 nF C1 needs ~1 second to discharge from 50V to 40V through 10M.

Let's assume there is no Q3/R5 in our scheme. How should the BQ76200 switch off the discharge FETs if DSG only goes down to BAT potential (assuming a load at DISCHARGE, there would be ~ BAT - 5V)?

Hi Dario,
The bq76200 is designed to control FETs in a common drain configuration as shown in the data sheet. The CHG and
DSG pins behave differently. CHG swings beween VDDCP and BAT pin voltage. DSG swings between VDDCP and the PACK
pin voltage and it can follow the PACK pin to 0V.

The bq76200 can not directly support FETs in a common source configuration. If using CHG to control the gate of
the discharge FET, when off CHG will not go below BAT leaving the discharge FET operating as a source follower
with the source voltage approximately Vgsth below BAT (your last question). The DSG driving the discharge gate
would initially seem to be OK since it can swing from 0 up to VDDCP. If there is no load DSG will pull up the FET
gate and the source through the 10M resistor. Normally the load current from the 10M resistor is 10V/10M = 1uA. If
there is a load on DISCHARGE and no charger on CHARGE, if DSG were to rise to VDDCP at 50V as proposed, the load
would be 50V/10M = 5uA which would be within the capability of the charge pump, however the FET would not be happy
with a 50V Vgs. Also there is an internal clamp which will prevent the rise of DSG more than about 20V above the
PACK pin. The CVDDCP will discharge into the clamp and the driver will turn off and cycle.

To have a high current discharge path with a discharge protected charge path, one bq76200 could control the large
discharge FET while a second bq76200 controls both (small) common drain charge and discharge FETs. Obviously
this is undesirable due to the cost, size and expense of the 2 drivers and 3 FETs.

As noted it may be possible to add a circuit to allow the common source charge FET gate (your Q3) to fall below
CHG. Consider a P-channel FET between CHG and BAT pins. If the charge FET needs to turn off fast consider a
circuit similar to figure 3 of www.ti.com/lit/slua795. Preventing turn on of CHG if CHARGE (the charger voltage)
is not present through system behavior should avoid dissipating the charge pump into an external gate clamp.
I've not tested a common source circuit, the part is recommended for common drain implementations.