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UCC24612: Why the turn on delay is so long -150ns for -2 version

bull power
Prodigy 10 points
Part Number: UCC24612
Other Parts Discussed in Thread: UCC28780,

Dear Sir,

I am looking at your solutions of ACF with UCC28780 and UCC24612.

I have a question about UCC24612-2

On page 12 of UCC24612 datasheet, there are such descriptions of 

"For certain applications, this delay is essential for appropriate operation. In Active Clamp Flyback, especially when the primary side switches are using Si based super junction MOSFET, due to the large nonlinear junction capacitor, the SR often sees a leading spike current, follow by the real conduction current. Normally, a prolonged minimum on time can override this spike to make the circuit operate normally. However, this causes large negative current that transfer the energy from output to the input and reduces the overall converter efficiency"

I understand that the superjuction Fet has a very big variance of Coss in low Vds and high Vds. But i don't understand why it will cause leading edge spike so that you make UCC24612-2 to have prolonged turn on delay?

Are there any waveforms could help explain the leading edge spike?

Br

  • 0
    TI__Intellectual 1615 points

    Hi,

      The leading edge spike of the ACF using Si super-junction MOSFET as the primary side switches is caused by the non-linear capacitor of the Coss. Si-based MOSFET not only has larger Coss, the Coss is also very non-linear.

       This non-linear capacitor makes the switch node rise slow at beginning of the low side turn on, when the switch node voltage is low. And then the voltage rising rate gets pretty fast due to the smaller Coss for both high side and low side switches, when there is voltage on them. Then the voltage node rise rate slow down again due to the large Coss of high side switch when its voltage reduces.

      When the voltage rising rate is fast, it pushes the current to the secondary side and force the current rise in the SR. When the switch node slows down, the secondary side voltage pushes the current back and make the SR current reduce.

      We had done some simulation and experiment to see the variation of this leading edge spike. It turned out 150ns is about the time we need to ignore the leading edge spike.