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LM5104: LM5104M

zacharias brandt
Prodigy 250 points
Part Number: LM5104

Hi, the enclose scope picture shows the output signal at OUT and with no load at all.

Why this distorted rising egde? Vdd is 13.1V

Why is the waveform not a direct square wave but have this slope after 10V? Supply is 13.1V

t

  • 0
    TI__Mastermind 21915 points
    Hello Zacharias,
    Thank you for your interest in the LM5104. I am an applications engineer in High Power Driver product line at TI and will work to address your questions.
    To better help explain the waveforms I need to ask some questions on the test conditions. The OUT waveform shown, is this the LO to VSS signal or the HO to HS signal? When you mention no load at all, is this no load on the power converter, or is there no load on the driver where Q2 and/or Q3 FET gates are disconnected from the driver?
    Was VDD at the 13.2V level when the driver input signal rising edge occurred? It looks like the driver bias is still rising after the rising edge.

    Regards,
    Richard Herring
  • 0
    TI__Mastermind 21915 points
    Hello Zacharias,
    I responded to your post on Nov 15th with an inquiry about more details on your test conditions to help resolve your concerns on the LM5104. Have you been able to determine the cause of the gate drive slow rise time, or confirm the test conditions I asked about in the Nov 15 response?

    Regards,
    Richard Herring