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BQ76930: 【Cell Balancing】first Balancing failed

Kevin Li
Intellectual 300 points
Part Number: BQ76930

Hi ~~

My BQ76930 can't open the  single cell balancing at the first time.

I have to guarantee my passive balance Current average value.  

The period of balancing Command is 500ms.   

(Client do not accept  period to be 1s  .I used set 1s before.But they don't like it.  And period 1s had this problem too. )

But It works when I both set CB1 & CB2.   Other Adjacent cells can work too.

And I find that each of the  CELLBAL1 (0x01)   、  CELLBAL2 (0x02)   had this problem.

1.  In following separate case.  Will happend this kind of problem

Case CB1 CB2 CB3 CB4 CB5
1 V 　 　 　 　
2 　 V 　 　 　
3 　 　 V 　 　
4 　 　 　 V 　
5 　 　 　 　 V
6 V 　 V 　 　
7 V 　 　 　 V
8 　 V 　 V 　
9 　 　 V 　 V
10 V 　 V 　 V

2.In following separate case.   will be good

Case CB1 CB2 CB3 CB4 CB5
1 V 　 　 V 　
2 　 V 　 　 V

P.S.

Bq76930 balancing period is 246ms



Thank you !!!!

  • 0
    TI__Mastermind 25955 points
    Hi Kevin,

    Please refer to 7.3.1.1.2 of the datasheet: www.ti.com/.../bq76930.pdf

    For each contiguous set of five cells (VC1 to VC5), when no cells in that particular set are being balanced, each cell is measured over a 50 ms decimation window (all zeros in the register). When at least one of the five cells (VC1 to VC5) are being balanced, each cell is measured over a 12.5 ms decimation window (at least one 1 bit in the register).

    Could you please repeat your test in your second image where you flipped states of CB1 = 1 and CB2 = 0 to CB1 = 0 and CB2 = 1, but look at the first capture.

    Please try a few sequences where
    (1) 10 commands are sent of all zeros CB1 = 0, CB2 = 0, followed by CB1 = 1 and CB2 = 0
    (2) 10 commands are sent of all zeros CB1 = 0, CB2 = 0, followed by CB1 = 0 and CB2 = 1

    You should see the same 'latency' effect in the first image, but for RCB1 and RCB2, respectively.

    The device should show the same waveform as the decimation period changes from 50 ms to 12.5 ms when the register goes from all zeros to always having at least one 1 bit in the register.

    Sincerely,
    Bryan Kahler