TPS22953: About behavior of Power Good

Hide

Part Number: TPS22953

Hi Team,

We understand that Power good pin is open drain which will pull low when the voltage on EN and/or SNS is below their respective VIL level.

Does Power Good maintain Low even if Vin is 0V or open and VOUT is around 3.0V?

Regards,

Kanemaru

over 6 years ago

0 Aleksandras_Kaknevicius over 6 years ago

TI__Genius 15740 points

Hi Kanemaru,

If EN is kept low (as in the diagram above) then the PG pin should not be pulled high.

Thanks,

Alek Kaknevicius

0 Hide over 6 years ago in reply to Aleksandras_Kaknevicius

Guru 21045 points

Hi Alek-san,

Thank you for your prompt reply.

Thank you for the information.

Regards,

Kanemaru

0 Hide over 6 years ago in reply to Hide

Guru 21045 points

Hi Alek-san,

I have one more question.

I understand that Power good pin is open drain and would like to know the control circuit(control logic) of Power good(PG).

Because, our customer concern that PG pin goes to Hi-z at VIN=0V or open, VOUT=3.0V.

So, they would like to whether PG maintains Low(FET of PG is ON) even if VIN=0V or open.

Could you please disclose this control circuit?

If you contact to below my e-mail address or let me know your e-mail address,

I can send the customer information.

I’m looking forward to hearing from you.

[my e-mail address]

Kanemaru-h@macnica.co.jp

Regards,

Kanemaru

0 Aleksandras_Kaknevicius over 6 years ago in reply to Hide

TI__Genius 15740 points

Hi Kanemaru,

I have reached out to our designer for additional details and will be able to get back to you this week with additional information.

Thanks,

Alek Kaknevicius

0 Hide over 6 years ago in reply to Aleksandras_Kaknevicius

Guru 21045 points

Hi Alek-san,

Thank you for your response.

I’m looking forward to hearing from you.

Regards,

Kanemaru

0 Aleksandras_Kaknevicius over 6 years ago in reply to Hide

TI__Genius 15740 points

Hi Kanemaru,

In the case where VIN, VBIAS, and EN are all 0V, and VOUT is powered, the device actually gets its power from the VOUT pin. By using the voltage on the VOUT pin to bias the device, the PG pin can be kept low.

Thanks,

Alek Kaknevicius

0 Hide over 6 years ago in reply to Aleksandras_Kaknevicius

Guru 21045 points

Hi Alek-san,

Thank you for the detail information.

I understand. Thank you very much.

Regards,

Kanemaru

Power management

Power management forum

TPS22953: About behavior of Power Good