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TPS650830: TPS650832, Internal Clock

Part Number: TPS650830
Other Parts Discussed in Thread: TPS650832

PMIC support team

I would like to know about the internal clock.

[1] What kind of oscillator does TPS650832 have as the internal reference clock? RC oscillator and so on.

[2] What is the internal cock frequency?

[3] What is the accuracy of the internal clock?

Thanks

Tamio

  • Tamio_Y,
    Thank you for using E2E. I have forwarded your question to a product specialist. You should hear from someone shortly.
  • Hi Tamio,

    The TPS65083x internal clock is an RC oscillator of 32.768 kHz. Accuracy is not specified for this device, but other similar devices had +- 10% as the internal oscillator accuracy.

  • Hi, Kevin

    Can you show the circuit of RC clock oscillator to me?

    As for Emergency Shutdown, the datasheet is mentioned as follows;
    It is initated when PWRBTN held longer than the defined time by Resister FLT[5:0].
    Is it possibility for TPS65983x to misdetect the period that PWRBTN is held to LOW?

    Thanks
    Tamio
  • Hi Tamio,

    Can you describe the issue being observed in more detail? It sounds like the concern is that PMIC is detecting a PWRBTN FLT (long key press) before it is supposed to.

    1. Do you have any scope shots of the issue you can provide that would help me to understand?
    2. Are the FLT bits being modified at all?
    3. What is the observed PWRbTN hold down time vs. when FLT is generated or is PWRBTN FLT being generated when PWRBTN is not being held down?
    4. Is "FCO" bit in RESETIRQ1 set after an unexpected shutdown?
    5. Are any of the other bits in RESETIRQ1 and RESETIRQ2 set?

  • Hi, Kevin

    Unfortunately, my customer tried to dupicate the same behavior, but they could not duplicate it yet.

    They said that the system caused the abnormal shutdowm when they pushed the power bottun.

    In other word, the system shutdowm occurred in the period shorter than the register configuration.

    1. Do you have any scope shots of the issue you can provide that would help me to understand?

    ➜Can't deplicate

    1. Are the FLT bits being modified at all?

    ➜oc checking

    1. What is the observed PWRbTN hold down time vs. when FLT is generated or is PWRBTN FLT being generated when PWRBTN is not being held down?

    ➜oc checking

    1. Is "FCO" bit in RESETIRQ1 set after an unexpected shutdown?

    ➜oc checking

    1. Are any of the other bits in RESETIRQ1 and RESETIRQ2 set?

    ➜oc checking

    I will update tomorrow.

    Thanks

    Tamio

  • Which of the following circuit structure is used for the internal RC oscillator?

    Or, is the other circuit structure used?

    Phase Shift Oscillator

    Twin-T Oscillator

    Thanks

    Tamio

  • Hi Tamio,

    It is a custom design based on the single ramp relaxation oscillator concept. I cannot provide further information regarding the internal IP of the chip.