TPS568215: min and max of internal enable delay and internal soft start time

The value is typical in datasheet. If you wanted to know the max and min, it may have a range because of different temperature and external condition. Why did you want to know this and what 's your application?

Application is FPGA core supply. Sequence is complicated for power-up and power-down. The hot-plug feature enforce additional constrains. Sequence timing have narrow timing windows. That is why I must to know borders. Please characterise min and max delays.

Your mentioned characteristic min and max delay varies according with different condition. Just consider the typical value when doing design.

Typical value is useless for me. I will not know if in mass production the design will be good. I understand that what I asking is under some function of use case. But i need only extreme values under such conditions: ambient temperature 0..85 deg.C. Vin=12V. Capacitor at VREG5 pin=4.7uF. What other conditions you need?

When can I expect an answer?