• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 63 subscribers
  • Views 576 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM5175: LM5175 Synchro Management of Boost Highside

peter koenig
Prodigy 30 points
Part Number: LM5175
Other Parts Discussed in Thread: LM5176


Hello,

my problem is that the boost highside synchro only works sometimes.

There is no influence of mode, boost 18 to 25V or buck 25 to 18V, temperature, current 0…6A.

But often it works in the whole range if the input voltage is reduced to 6V before.

 

How is the inductor current drop to zero for the disabeling of the synchros detected?

What could be the reason?

 

The layout is nearly the same as in your EVM SNVU440.

The 8V2 zener diodes are integrated.

 

Thank you very much for your help

Best regards

Peter


  • 0
    TI__Guru* 78070 points
    Do you mean the boost leg sync FET does not switch? Could you show the waveform of the gate drive signal under different Vin and Vout conditions as you mentioned above?

    If I understand your second question correctly: There is a zero crossing detection of the inductor current (by means of the current sense signal). When the inductor drops zero, the sync FET is turned off, emulating the regular diode just allowing unidirectional current flow.
  • 0 in reply to Youhao Xi
    Prodigy 30 points

    Hello,

    yes, the boost leg sync FET does not switch.

    Attached you can see some plots.

    In boost mode the zero crossing of the inductor current can not be seen at the common source shunt or the output shunt.

    Is the time calculated from the maximum voltage at the common source shunt at the end of the pulse before and the relation between input and output voltage?

    In this case I think that the only point I perhaps could  find something would be the shunt Signal.

    Or is there an influence of the ISNS Regulator? I have seen that at 6V input voltage , the current regulation at the ISNS is no more working. So the over voltage regulation at FB is active and after that the boost leg sync FET works correctly.

    Thank you

    Peter

    plots of boost hs synchro problem LM5175.pdf

  • 0 in reply to peter koenig
    TI__Guru* 78070 points
    Thank you for the info. These waveforms look strange because the inductor current must continue and appear as negative voltage across the common source shunt. Could you show your own schematic for us to review?
  • 0 in reply to Youhao Xi
    Prodigy 30 points
    Hello,

    the schematic I should send you on another way.

    But here are some news.
    One reason for HDRV2 mismanagement is the use of the current limiter ISNS because it reduces the soft-start. See 8.3.13 “The gate drive output HDRV2 remains off during soft-start to prevent reverse current flow from a prebiased output”.

    This is conflicting with 2 Application “Backup Battery and Supercapacitor Charging” and 8.3.6 “The average current limiting feature can be used in applications requiring a regulated current from the input supply or into the load” because without synchro mode it can be used only for a very short time.

    Another big problem is that in all of the 4 modes it converts power from the battery output to the PSU input if the output voltage is higher than the programmed level. This easily can happen if microcontroller and current regulator work.

    In datasheet of LM5176 there are only 2 of the modes possible and the above sentence in 8.3.13 is missing.
    But there is nothing specified to this problem.

    So I have to come back to my old question:
    In boost mode the zero crossing of the inductor current can not be seen at the common source shunt or the output shunt.
    Is the time calculated from the maximum voltage at the common source shunt at the end of the pulse before and the relation between input and output voltage? In this case I think that the only point I perhaps could find something would be the shunt Signal.
    Or does it depend on the comp signal

    Do you have another solution?

    Best regards
    Peter