We have an application of the LM5117 where a number of converters are being run in parallel. Sometimes they run in current limit and sometimes they are lightly load and some phases are disabled by applying a low (GND) signal to the UVLO pin. The input to the system is ~ 32V and the output is ~ 26V (Power Mosfet bridge is tied to 32V). The Internal regulator is disabled and an external 12V is applied to both VCC and VIN.
When one of the converters is turned off via the UVLO pin, the RAMP pin is driven above the 7V ABS max through the ramp pin resistor as it is tied to the common 26V output voltage. The voltage at the ramp pin is measured at ~ 12V with a current limit of about 80uA worst-case. Perhaps there is an ESD diode clamping things to Vcc?
The block diagram appears to indicate that the RAMP pin would be held low with an internal FET when the high switch is off but this is not happening.
Questions (2):
1. Will the device operate reliably with the RAMP pin pulled above the ABS max considering that the current is limited to ~ 80uA? IS there any low level of current that would be acceptable?
2. If the UVLO were pulled to, say 0.8V (Standby mode), would the RAMP pin be held low by the internal open-drain device?
