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WEBENCH® Tools/TPS61087-Q1: Slope compensation, oscillations on webench bode simulation

Part Number: TPS61087-Q1
Other Parts Discussed in Thread: TPS61087,

Tool/software: WEBENCH® Design Tools

I am running the bode simulation in the webench of the TPS61087-Q1 and see a high Q peak at half the switching frequency, which I would expect if I would have a standard current mode control boost converter with >50% duty cycle and no slope compensation. However, there is no mention of slope compensation in the TPS61087-Q1 datasheet and it also completely disregards this additional pole to consider when designing the compensation network. Further to this, earlier versions of the TPS61087 datasheet explicitly mention that:

"Because of the quasi-constant frequency behavior of the device, the TPS61087 eliminates the need for an internal oscillator and slope compensation, which provides better stability for the system over a wide of input and output voltages range, and more stable and accurate current limiting operation compared to boost converters operating with a conventional PWM scheme."

Thus: Does the model of the TPS61087-Q1 in webench reflect this behavior of the chip in the bode simulation, or does it act as a standard PWM controller and therefore lead to wrong results? 

Attached the esim report from webench...

webench_esim_4961223_36_15_328233384.pdf

 

  • The phase margin is higher than 60C at the cross over frequency. So the system is stable. 

    You can add a pole from the COMP to the GND, that is: add a 100-220pF cap from the COMP to the GND then simulate again.

  • Thanks, but I wasn't asking "is my design stable?", but rather was surprised by the occurrence of the subharmonic oscillations in the result of the bode simulations, which I think disagrees with how the chip is presented in the datasheet: I thought these oscillations are already dealt with by the internals of the chip design and is somehow indicated in the datasheet (presented as a fixed or adaptive "off time"). If the chip would not deal with it internally, I would expect that it would support a way of applying slope compensation to the measured inductor current signal, to avoid this kind of behavior, but nothing like this is mentioned in the datasheet.

    As I have no way of measuring the loop gain on the real PCB of this chip, I would like to know if the model used in the bode simulation is correct, as it disagrees with what I think is presented in the datasheet?

    PS.: Nevertheless, I will try to add the additional pole to the compensation network, however, webench is not very user-friendly in doing so (it gets stuck when trying to edit the schematic in a new editor window, when I want to freely edit the suggested topology of this converter design), and the TINA designs (as far as i know) only allow transient simulation...

  • For the TPS61087, it rely on the external compensation since there's a COMP pin. And reduce the value of Rcomp also helps.
    I can test a real bode plot for you if you need it.
  •  The real bode plot is different with your simulation result. Please check the attached file. So the Webench model needs to be updated.

  • Hello,

    Thanks for going through the effort and testing the real loop gain of the device. I just want to confirm, the above result you attached, is that with the same compensation network and power stage as I have attached in my webench results in the first post?

    Can you envision when the webench model will be updated?

    Best regards,
    Christoph
  • Yes, I use the same parameter as what you used in your first post sch. The modeling team is a totally different team. They need at least 1-2 month to update the model.
  • Thanks a lot for your information. Is it possible to see the revision history of webench models or at least, what their last date of change was? Is there somewhere a bug-tracker for models?
    Maybe would be worth mentioning this disagreement of model and real world for this part in webench.

    Best regards,
    Christoph
  • Good sugestion, I'll assign this post to sahil, he can answer your question.
  • Hi Christoph, Yes we have entered this issue into our internal TI bug JIRA tracker, and I am working on it to resolve the model. 

    Will let you know once this is released to ti.com/

    thanks for your suggestion, 

    sahil