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BQ76PL455EVM: Vdig capacitor issue

Rohan Patwardhan
Intellectual 260 points
Part Number: BQ76PL455EVM

Hi All,

I am currently working on BQ76PL455EVM. I am monitoring 16 cell voltages. When connected to GUI, the GUI does open, but when cell voltages are polled, I am getting 0V for all cells. I observed voltages at Vdig and Vm pin and both were 0V. I checked the capacitors at both pins. They had not short circuited. However I still replaced them but got no success. Does this mean that the chip has blown?

Regards,

Rohan

  • 0
    TI__Genius 11480 points
    Hi Rohan,

    Is this with our EVM or did you make a board?

    How are you connecting to the GUI? If VDIG and VM are 0, it sounds like the part is either not awake or has been damaged. What is the voltage at VP?
  • 0 in reply to David Wiest Jr
    Intellectual 260 points

    Hi David,

    I have actually made a board having two interfaces, one for GUI and one of microcontroller. I am first checking the GUI interface, before moving to microcontroller.

    When I first tested the board, I did get all cell voltages. The next time I powered up the board is when I got 0V for each cell. I checked the BJT output. The collector was at TOP pin voltage while emitter was at 0V. I am assuming that the transistor has not switched at this point. Will changing the transistor help?

    Another observation in the GUI was that I was getting a VDIG wake fault in GUI. Does this observation help in determining if chip is damaged or transistor is an issue.

    Thirdly, If we supply a regulated 5V to Vp pin, the IC should still work and we can eliminate the BJT circuit if we find it unstable.

    Lastly, I have followed the EVM reference schematics for developing the PCB. One error from my side is that  C36 as per EVM is rated for 25V and not 50V as mentioned in EVM. Could this be a problem as well?

    Regards,

    Rohan

  • 0 in reply to Rohan Patwardhan
    TI__Genius 11480 points

    Hi Rohan,

    VDIG wake fault indicates that that the VDIG rail did not ramp up/down correctly - probably  due to increased leakage into the pin. If there is a malfunction with VDIG, the digital core may not function properly, which explains the odd readings.

    I would try to replace the transistor first. I think the VP regulator is a likely candidate for where things went wrong. I would caution against  using an external regulator. This is technically possible, but there is more room for error, since the proper supply sequence must be maintained.

    For the cap, it should be okay i think. 

  • 0 in reply to David Wiest Jr
    Intellectual 260 points

    Hi David,

    Thank you for your response. I have made an observation but could not fully understand it. I followed the power up sequence as follows:-

    1)Power given to BAT16

    2)Power given to BAT0

    Once, this was done, I checked the GUI and it opened. Now polled cell voltages, without cell inputs connected. I was getting garbage values for all cells. Then I stopped the polling and opened the GUI again and did the same and this was when I got 0V for all cells. Could you explain this observation? Should cell voltages not be polled if any cell input is disconnected? 

    Regards,
    Rohan

  • 0 in reply to Rohan Patwardhan
    TI__Genius 11480 points

    Hi Rohan,

    This is somewhat un-intuitive, but expected. The leakage  current from the caps/diodes cause the filter capacitors to charge up. If you plot this over time  you will originally see all of the cell voltages  scattered, as the voltage  is undefined. Once the caps are charged the voltages will converge (at least somewhat closely) to each other. If you turn on the balance FET you would see this voltage drop as the charge held in the filter caps bleed off.