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TPS659037: Power on sequence issue

chentsu chung
Mastermind 6180 points
Part Number: TPS659037

Hi,

I'm using TPS6590376 and here's the power on sequence testing resule

According to the power on sequence table from datasheet as below


Here's the questions:

1. What is the max./min./typ. value for the 550us time sequence?

2. For all sequence, only LDO2 less then 550us, is this normal?

3. Following question2, if it's abnormal, how to modify it?

Thank you.

C.T.

  • 0
    TI__Genius 16410 points
    Hello CT,

    The 550us delay is based on the internal 32k clock, and therefore is +/- 10% accurate. So the 504us you measure is within the range.

    There are also some internal analog delays in the LDO or SMPS module before it starts ramping up from 0V. So it is common to see additional +/- 100us delay before some rails. In my testing, LDO2 comes up about 100us before LDO3 and LDO4, so this is normal behavior. You will see the same variation between LDO9 (VDD_RTC) and LDOLN (VDDA_PLL).

    Note that LDOUSB has an internal 215us delay, so you will see an extra delay on that rail as well.

    Regards,
    Karl