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BQ76940: BQ76940 doesn't communicate via I2C

Part Number: BQ76940
Other Parts Discussed in Thread: TIDA-00449, , TIDA-00792

Dear Sir,

we have a problem regarding to the design of the new BMS slave module for 13S LiIon cells.

The design is based on TIDA-00449 and chip's datasheet, however, we have a problem as chip doesn't start to communicate. REGSCR as well as REGOUT are not connected as well as SRP, SRN, CHG and DSG pins as this module is only used for monitoring (and balancing) and does not have any power FETs (or need to measure current).

Please find attached AFE schematics, pullups on I2C are on the other (MCU) sheet, but they are mounted.

3225.Schematic Prints.pdf

  • One more information / question:
    After enabling BQ (short-connect on BQ_enable pins), LD10 is slightly lit (between VC10x and VC11) - any idea why?
    Tried on 3 different board, BQs were replaced with new ones etc. - still the same.
  • Hi Gregor,
    REGSRC is a power pin and must be powered or the part will not work. R47 would allow connection to cell 13, but this would be too high of a voltage and would damage the bq76940. You will need a voltage within its range. You don't show CHG and DSG used so something between minimum and about 15V should be fine if you have a regulated voltage available, or use something like the source follower shown in the data sheet, EVM, or reference schematics. REGSRC should have a filter capacitor.
    REGOUT is powered from REGSRC and is used for internal circuits also. It must have a capacitor even if not used externally, see the data sheet
    The bq76940 BAT pin does not show a power connection, the upper group would receive power only through D1 loading the VC15 input. You should have a connection to C13f with a 1k filter resistor similar to R26 at VC10x.
    I don't find power filter capacitors on the schematic sheet, there should be 1 for each group, 10 uF is typical, see the data sheet, EVM, or reference schematic. The part may not operate properly without power filter capacitors.
    In the schematic there is a line connecting the bottom of C4 to the bottom of C6. This line should actually be a capacitor of the same value. The right sides of R21 and R25 should connect together (VC10B). The same correction needs to be made at VC5B/VC5X. This and the missing power to the upper group may be the reason the LED glows when the part is booted.
  • Dear Sir,

    many thanks for your answer. I did all the steps (I hope) - could you please review the schematics?

    I applied those on a current prototype (doesn't look nice but hopefully shall work ;) ) - will see soon ...

    I would suggest adding a remark to the REGSRC pin in the datasheet that it needs to be connected? Regarding to the internal block diagram (7.2) it is not clear, if REGSRC is needed in case of oxternal power supply ...

    0474.Schematic Prints.pdf

    Regards,

    Gregor

  • Hi Gregor,
    Somehow we got confused and there are extra capacitors/wrong connections at C33, C39, and C18. I guess the capacitor was there and the connection was wrong. See TIDA-00792 for example connections.
    You may want or need blocking on REGSRC for brownout conditions. See the various schematics and possibly the section in the Top 10 Design Considerations apnote.
  • Huh, now I really am confused! :)
    I can see about C33 and C39, as I compare the schematics from TIDA and mine, I see C33 and C39 should not be there. But I am confused about C18: as I look at TIDA, the capacitor is there (C22 in TIDA) ...
    Anyway, now the BQ is communicating with the MCU, working on tests now ...

    Regards,
    Gregor
  • Most tests passed so far (voltage read); I removed C33 and C39, but leace C18. I also add 100 nF at REGSRC.
    One question regarding to balancing: as some cell groups are connected together in 13S configuration (8+9 and 13+14), I assume that both pins must be activated when balancing this cell. Is this correct (or are those pins HiZ, so activating only one is also fine)?
    Another question regarding to balancing: regarding to datasheet not all (well, n-1) cells can be balanced at the same time. What is the prefered method to do the balancing; I was thinking balancing cells in 2 groups (odd and even) - is this ok from the design view? (balancing power isn't an issue)
  • Hi Gregor,
    You found something the designers and reviewers missed, thanks. The lower side of C18 in your schematic connects to VC0, as does C22 in the TI design. This is actually not the preferred connection, notice figure 8-3 in the bq76940 data sheet and figure 34 in the slvu925 EVM user guide. The other TIDA-00449 for the family also has the incorrect connection. The VC1 capacitor to ground rather than VC0 avoids pushing VC0 below VSS during load transients on the battery where all inputs pull the filter low. Apparently the TI Designs worked acceptably, but I would recommend connecting the VC1 cap (your C18) to VSS.
    For balancing only the cell to be balanced needs to be activated. The pins on the unused cell are high impedance, but are low impedance with the external connection (such as VC13 and VC14 shorted).
    Adjacent cells should not be balanced simultaneously (data sheet section 7.3.1.3.3). Yes, odd and even balancing is OK, use the odd/even numbering of the connected cells. For example with VC13 and VC14 shorted do not simultaneously balance cells 13 and 15 of the IC since they are physically connected as adjacent.
  • Many thanks for your help and support!
    So far everything works, measuring, balancing etc.

    Regards,
    Gregor