UC2875: External Sync

Mark Holleman

Part Number: UC2875

The data sheet doesn't give any specifications for this signal, but page 10 shows a very short pulse driving a pull-up FET. Page 14 also shows very short clock pulse. Can you tell me if this signal is required to be this short? if so how short does it have to be? Also, is the resistor and pull-up switch required, or can the input be driven to ground?

over 7 years ago

0 Benjamin Lough over 7 years ago

TI__Mastermind 27105 points

Hi Mark,

thanks for your interest in UC2875. The CLK IN parameter is an internal signal on the IC. Figure 10 is illustrating how to use this device with voltage mode control.

Best Regards,
Ben Lough

0 Mark Holleman over 7 years ago in reply to Benjamin Lough

Prodigy 30 points

Thanks Ben,
Do you know what the limitations of the input signal as shown in figure 6 are? What pulse width and pull down resistance are recommended?

0 Benjamin Lough over 7 years ago in reply to Mark Holleman

TI__Mastermind 27105 points

Hi Mark,

The pulse width and pull down resistance are internal to the IC and are not set by the designer. As long as you stay below the maximum frequency of the device, the equation provided for voltage feed forward will be valid.

Best Regards,
Ben Lough

0 Mark Holleman over 7 years ago in reply to Benjamin Lough

Prodigy 30 points

OK Thanks, TI should really clarify the "Syncing to External TTL/CMOS" section.

0 Benjamin Lough over 7 years ago in reply to Mark Holleman

TI__Mastermind 27105 points

Hi Mark,

Apologies, I misunderstood your original question.

The maximum pulse width on the SYNC pin must be below 100ns. The amount of resistance needed on the SYNC line depends on how much parasitic capacitance there is on the SYNC trace. This resistance is not required but is recommended.

Apologies for the confusion.

Best Regards,
Ben Lough

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UC2875: External Sync