Part Number: LM5116
Dear Team,
my customer would like to know how the device behaves in conditions when Vin < Vout.
Design Parameters:
- Designed Input Voltage: min. 9V
- Designed Output Voltage: 7V
- Input Caps: 4* 4.7 uF
- Output Caps: 4* 10uF
Now the situation that the input voltage goes down to 6V, so Vin < Vout.
Can we assume how the system will behave?
On the one hand, I assume that the UVLO mechanism will send the device into a Sleep Mode at a certain voltage. On the other hand, the external FETs might have body diodes and the body diode of High-Side FET could be conducting.
Once I had a situation with a High-Side FET system protection where the input voltage was collapsing and with smaller C_in compared to bigger C_outs, the body diode was conducting.
Any feedback is very much appreciated.
Best Regards
Martin
