TPS737: Could you tell me about TPS73701's suspicious behavior?

HI Pokkun,

The rise time you are using is very slow. What is happening is when VIN is ramped slowly, it is below the target regulation VOUT so the LDO will be operating like a switch, it is over-driving the gate of the pass- FET in the attempt to regulate VOUT (i.e. minimize RDSON of the FET). During this time, the Gate of the Pass-FET is likely clamped to ~6V. When VIN finally is high enough to properly regulate VOUT, Our error amplifier engages and tries to take control of the pass-FET by pulling charge off of the gate to get the Pass-FET into linear region to dynamically adjust the drop across so it can regulate the load. This control loop has some small delay which is what I believeyou are seeing.

Thank you very much for the reply, John Cummings-san.

＞The rise time you are using is very slow.
⇒Isn’t it a mistake of "very fast"?
※The data sheet is 180 msec, customer data is 20 msec (within visible range).

Please let me ask a question for confirmation.
Q１：In other words, by slowly raising the power supply, the difference voltage occurs from the operation start the internal circuit to the start of the regulation operation.
Does mean that the difference voltage also behaves at VIN = VOUT?
（Is my understanding correct?）

Q２：If "Q1" is correct, what is the countermeasure method thought one of the followin, is it correct?
(If you have any other good ways, please let me know in addition.
① Slowly raise the power supply (VIN = EN) over 150 msec.
② Start up VIN and EN separately, turn on EN after turning on VIN.

Q３：Also, since I got the customer's circuit diagram, I also want you to confirm that there are no other factors from the viewpoint of the circuit.

Best regards,

Masumi Sekiguchi

HI Sekiguchi-san,

Thank you for sharing more details. Let me try to answer your questions below. With respect to 'very fast' ramp of VIN, the TPS73701 has a built in current limit. So we can product ourselves by limiting the current into the load capacitors.

For Q1: I believe your understanding is correct in that If any LDO's target output voltage is greater than the input voltage, VOUT=VIN-RDSON*ILOAD.

For Q2: Option #1, We have to run some tests, but I think any time you are slowing ramping VIN with VEN pulled up to VIN, the gate of the Pass FET will have its maximum voltage trying to regulate VOUT. So slowing down the VIN Ramp is not likely to resolve the issue. Option #2. Yes Ramping up VIN first, then enabling the device should work. In this mode, we have to turn on the internal charge pump and ramp up the gate voltage so in this mode the overshoot, should be minimal.

For Q3 : Adding C1503 (it does not appear to be used currently) Might help the issue you are seeing but will help to improve PSRR and transient response. It is not always easy, but following the EVM layout as closely as possible, is highly recommended.

I hope this helps. Please let me know if you need further clarification.

I’m sorry to late contacting.

First of all, I understood about the answers to Q1, Q2, Q3.

Next, on the point that I asked 「Is not it a mistake of" very fast "?」, The waveform in Figure 23 of the data sheet is 2 msec / div for 50 msec / div.

Comparing the behaviors at startup, I think that the customer's waveform and the red frame below are the same,

so when comparing the time axis of this point, I felt that the customer waveform started " very fast ".

Is my opinion wrong?

I’m sorry for my lateed contact, but can you give me a response my quesion again?