• State TI Thinks Resolved
  • Locked Locked
  • Replies 13 replies
  • Answers 5 answers
  • Subscribers 64 subscribers
  • Views 2686 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS544B25: TPS544B25 External Sync Clock

shashi kanth
Prodigy 250 points
Part Number: TPS544B25

Dear Sir,

Sub: TPS544B25 Regulator with external Sync clock,

Regulator input, output and current requirements.
Input Volts = 4.0V - 6.0V DC
Output Volts = 0.95V DC
Max Current = 20A

Architecture:
In our design we will power the regulator first with default setting, and this power is used for powering an FPGA,

Once the FPGA is powered,

On need basis we want to provide SYNC clock generated from FPGA to the SYNC pin of the regulator,

Kindly confirm, our method of providing SYNC clock is Ok,
Also when this SYNC clock applied, the regulator output voltage should not be altered.

In case any issue, Please advise us how to control the SYNC clock based on our present power tree,

Best Regards,
Shashi.

  • 0
    TI__Guru**** 191445 points

    Shashi,

    The datasheet section 8.3.9 contains details about applying the external clock,  The exact configuration depends on whether you are using the VSET function.  The external clock should be within 20% of the RT set frequency.  Changing the frequency mode on the fly can disturb the control loop and cause slight under or over voltage transients on the output.  Let me know if you need further information.

  • 0 in reply to JohnTucker
    Prodigy 250 points

    Dear John Tucker,

    Thank you for the quick response,

    Listed below with the details:

    VSET = 34.8K to AGND

    SYNC/RESET_B = Reset, Low signal to this pin then Voltage Output is Zero,

    To use Sync Functionality
    Using PMBUS, FORCE_SYNC bit in register MISC_CONFIG_OPTIONS(MFR_SPECIFIC_32) (F0h) should be set to 1


    Our Concerns:
    We plan to use External power good signal to SYNC/RESET_B pin to implement Enable/disable regulator output,
    Connecting a FPGA GPIO to SYNC/RESET_B pin to implement external sync functionality
    Concerns of Logic Conflict of Power good and FPGA GPIO signals on the same Pins.

    Is there a optimized and best solution for the above mentioned approach,


    Overshoot or undershoot Query:
    A sudden change in synchronization clock frequency causes an associated control loop response, resulting in an overshoot or undershoot on the output voltage.
    Query:
    a) how much would be the overshoot / undershoot and Kindly share test results references,
    b) What is the recommended ways to see that voltage overshoot / undershoot does not occur.

    Best Regards,

    Shashi.

  • 0 in reply to shashi kanth
    TI__Guru**** 191445 points
    Let me see if we have any data for it.
  • 0 in reply to JohnTucker
    TI__Prodigy 580 points

    Hi, Shashi-San,

    1. After the FORCE_SYNC bit is set and stored in EEPROM, the SYNC_IN function would be active whenever VIN/VDD voltage exceeds 3V around.

    2. When the FORCE_SYNC bit is NOT set, which is the default option, with 34.8k VSET resistor to AGND, the RESET_B function is active. When pulling RESET_B low during operation, assuming no voltage divider used on DIFFO-FB-GND connection, the output voltage would not be reset to 0, instead, the output voltage would be reset to the default VOUT_COMMAND value 0.95V which 34.8k VSET programmed.

    3. Neither the SYNC or RESET_B function is defined/implemented to support Enable/Disable function. To use power good signal for Enable/Disable function, power good signal need be routed to CNTL pin instead.

    4. To implement external sync-in function, the external sync clock need be within ±20% range of the internal oscillator frequency which is set by the RT resistor. Details can be found in datasheet section 7.3.8, page 24. During run time, “A sudden change in synchronization clock frequency causes an associated control loop response, resulting in an overshoot or undershoot on the output voltage.” This behavior or response cannot be avoid not only because changing operating frequency would change the ramp of the modulator as feedforward function is implemented in this device, also because the actual ON time is modulating results from compensation loop output and ramp signal.

    5. As explained above, the overshoot/undershoot level would be tightly determined by the compensator parameter and also the step of the sudden SYNC frequency change, it need be examined in a case by case basis.

    6. Suggested solution is using an I/O signal from FPGA or power good signal from other power rail feeding into CNTL pin to implement ENABLE/DISABLE function, while maintain a clock signal from FPGA to implement the synchronization function.

    Thanks.

    Best regards,

    Ray Chen

  • 0 in reply to Ray Chen
    Prodigy 250 points

    Dear Ray Chen-San,

    Thank you for the quick response, Info shared was useful,

    Is it possible to avoid using PMBUS interface with FPGA and meet below requirement.

    Design Requirement:
    1) External Power Good signal to control enable and disable function of the regulator.
    2) By default Regulator should power up with internal clock reference, After power up, should be able to Sync with external clock (±20% of internal clock frequency)
    Input Volts = 4.0V - 6.0V DC
    Output Volts = 0.95V DC
    Max Current = 20A

    suggestions to meet this requirement is welcomed,

    Best Regards,
    Shashi.

  • 0 in reply to shashi kanth
    TI__Prodigy 580 points

    Hi, Shashi-San,

    CNTL pin can be considered as an EN pin instead of part of PMBUS interface. Comparing to EN pin in other integrated power converting devices, you can consider CNTL as a digital input pin, on which the threshold is around 1.1V.

    1. External power good signal can be routed to CNTL pin to enable and disable operation.
    2. After the input voltage exceeds about 3V, all the internal digital functions starts functional. If the FORCE_SYNC bit was set and stored before the power up, then the device would be synchronized to external clock upon the detection of external clock.
    3. By default, the minimum VIN_ON voltage is 4.5V while minimum VIN_OFF voltage is 4.0V. You can configure the VIN_ON to the lowest value 4.25V through PMBUS. After power on, the device starts operation when input voltage is higher than VIN_ON, thus operating at 4V~4.25V is not applicable.

    Thanks.

    Best regards,

    Ray Chen

  • 0 in reply to Ray Chen
    Prodigy 250 points
    Dear Ray Chen-San,

    For our previous query, we have not got the inputs yet, so posting it again here, Kindly share the required details for below.

    Overshoot or undershoot Query:
    A sudden change in synchronization clock frequency causes an associated control loop response, resulting in an overshoot or undershoot on the output voltage.
    Query:
    a) how much would be the overshoot / undershoot and Kindly share test results references,
    b) What is the recommended ways to see that voltage overshoot / undershoot does not occur.


    Best Regards,
    Shashi.
  • 0 in reply to shashi kanth
    TI__Guru**** 191445 points
    Shashi,

    The voltage variation is very much application specific. It will depend on your actual design. Specifically the RT operating frequency, the external sync frequency, Vin, Vout, Lout, Cout and the compensation are all factors in the time domain response.
  • 0 in reply to shashi kanth
    TI__Prodigy 580 points

    Hi, Shashi-San,

    It's actually answered in previous reply:

    "To implement external sync-in function, the external sync clock need be within ±20% range of the internal oscillator frequency which is set by the RT resistor.

    Details can be found in datasheet section 7.3.8, page 24. During run time, “A sudden change in synchronization clock frequency causes an associated control loop response, resulting in an overshoot or undershoot on the output voltage.”

    This behavior or response cannot be avoid not only because changing operating frequency would change the ramp of the modulator as feed-forward function is implemented in this device, also because the actual ON time is modulating results from compensation loop output and ramp signal."

    In short, the response need be studied in case by case basis.

    Thanks.

    Best regards,

    Ray Chen

  • 0 in reply to JohnTucker
    TI__Guru**** 191445 points
    What is your SYNC frequency and RT set frequency? We can model this and get a representative waveform.
  • 0 in reply to JohnTucker
    TI__Guru**** 191445 points
    Shashi-san,

    I was able to model the external clock sync handover in pspice. I will post some details shortly.
  • 0 in reply to JohnTucker
    TI__Guru**** 191445 points

    Shashi-san,

    See the enclosed plots.  These are using the basic TPS544B25 model for 12 V in, 0.95 V out, 500 kHz Fsw and 20 A load.  at the 1.3 msec time mark I started an external clock.  you can see the voltage deviation at the output in the bottom trace.  File names show the frequency deviation. Let me know if you have further questions.

    trans_500 k to 480k zoom.pdftrans_500 k to 600k zoom.pdftrans_500 k to 400k zoom.pdf

  • 0 in reply to JohnTucker
    Prodigy 250 points
    John Tucker-san,

    Thank you for the support provided,

    Best Regards,
    Shashi.