UCC27210: Excessive ringing problem in half bridge configuration

Hi Luca,

Thanks for reaching out! I am an apps engineer working with UCC27210. Looks like a nice little circuit you got there. Can I ask you what application is the transducer for?

You mention HS ringing with higher highside drain voltages. Which fet is damaged HS or LS? Thats a great observation and could very well be exceeding the maximum HS mosfet Vgs or LS mosfet Vds caused by the switchnode ringing. A concurrent scopeshot of HS-GND and HO-HS would be helpful proving this. This ringing might make sense because as you increase the energy stored in the parasitic inductance and capacitance on the switch node, and when you turn on the HS fet after the freewheeling effect from the LS body diode load current (which charges the parasitic drain inductance of the LS fet) you are changing the polarity of LS drain and HS source parasitic inductance and discharging it into the switchnode the same time that the LS parasitic capacitance becomes charged from VIN. That charging and discharging on the same node creates a LC filter type ringing on the switchnode. You can read into more detail about this here: www.ti.com/.../slyt465.pdf

For a solution to this your best bet is to slow down the rise time the HS fet with a small gate resistor value. You can also put a cap in parallel with Cgs of the HS fet to create the same affect. If possible I would like to see a schematic of how your connecting the driver-fets-transformer piezo circuit.

Thanks,

Dear Jeff,

Many thanks for replying me fast and helping me. The fet that is always damaged in my application is the HS (already three times during my tests) . I have to limit the maximum voltage applies to the half bridge to work in safety condition. Looking at the voltage referred to gnd in the HS switching node this is clearly less than -20 V ( larger in absolute value) when the fet fails. The ringing amplitude is more o less similar during the rise time and fall time and its maximum amplitude is almost 100% of the applied voltage before dumping in few us.  The application is a standard driver circuit for a ultrasound piezoelectric transducer where high voltages are required to generate significant acoustic wave. Even if, in this application, where a transformer is used to amply the voltage on the secondary window, the control signal frequency is quite low (below 1 MHz), I have designed the circuit with fast driver and fast power fets because I would like to use the same structure also for high frequency applications (with high frequency transducers), obviously without using the transformer part that cannot be used for high frequency voltage signals. Below you can see the circuit . The primary window of the coil is connected between HS and GND or HS and the middle of two capacitors (if a positive/negative waveform is needed in the application). At the moment I am using the circuit with the primary connected to gnd. If I add a capacitance in parallel between GS in the HS fet I will reduce the rise time but also the fall time, maybe I have to add the same capacitance also in the low side to avoid a current path to ground during the switching phase.   Many thanks.

Luca